# US 12,009,250 B2 · Semiconductor device and a method making the same

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- Number: US 12,009,250 B2
- Document ID: US12009250B2
- Status: Granted
- Kind: B2
- Application number: 17/431,148
- Filed: 2021-03-26
- Published: 2023-04-20
- Granted: 2024-06-11
- Earliest claimed: 2020-05-20
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: ChangXin Memory Technologies, Inc.
- Inventors: Zhan Ying; Qiang Zhang; Yiming Zhu
- Web page: https://patentgrep.com/patent/US12009250B2

## CPC

- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/01: {Manufacture or treatment}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of first trenches;
forming a first pattern, wherein the first pattern comprises an array of lines each disposed between two adjacent ones of the plurality of first trenches;
forming a first dielectric layer, wherein the first dielectric layer covers at least sidewalls of the array of lines of the first pattern; and
segmenting the first pattern to form a second pattern, wherein forming the first dielectric layer covering the at least the sidewalls of the first pattern further comprises:
forming the first dielectric layer on the sidewalls of the array of lines of the first pattern and bottom surfaces of the plurality of first trenches, and
removing the first dielectric layer from the bottom surf aces of the plurality of first trenches, and wherein after forming the first dielectric layer covering the sidewalls of the first pattern and before segmenting the first pattern, the method further comprises:
forming a third dielectric layer in the plurality of first trenches, wherein the third dielectric layer fills the plurality of first trenches.

### Claim 2 (depends on 1)

The method of manufacturing the semiconductor structure according to claim 1, wherein a width of one line of the array of lines in the first pattern is less than or equal to 20 nm, and wherein a distance between two adjacent lines of the array of lines in the first pattern is less than or equal to 30 nm.

### Claim 3 (depends on 1)

The method of manufacturing the semiconductor structure according to claim 1, wherein segmenting the first pattern to form the second pattern further comprises:
dividing, with a plurality of second trenches, each of the lines in the array of the first pattern into a plurality of elements in the second pattern; and
filling a second dielectric layer in the plurality of second trenches.

### Claim 4 (depends on 3)

The method for manufacturing the semiconductor structure according to claim 3, wherein:
a material of the third dielectric layer is different from a material of the first dielectric layer, and
the material of the third dielectric layer is a same as a material of the second dielectric layer.

### Claim 5 (depends on 3)

The method for manufacturing the semiconductor structure according to claim 3, wherein:
a material of the third dielectric layer is different from a material of the second dielectric layer, and
a viscosity of the second dielectric layer is lower than a viscosity of the third dielectric layer.

### Claim 6 (depends on 5)

The method for manufacturing the semiconductor structure according to claim 5, wherein a maximum dimension of one of the plurality of second trenches in a plane parallel to the substrate is less than 15 nm.

### Claim 7 (depends on 3)

The method of manufacturing the semiconductor structure according to claim 3, wherein:
dividing each of the lines in the array of the first pattern into the plurality of elements in the second pattern comprises forming a mask layer on the first pattern, wherein the mask layer is patterned to include a plurality of openings penetrating through the mask layer, wherein the plurality of openings defines locations and shapes of the plurality of second trenches on the first pattern;
the shapes of the openings are circles, ellipses, or rectangles; and
the first pattern is etched based on the mask layer to divide each of the lines of the array in the first pattern into a plurality of elements in the second pattern.

### Claim 8 (depends on 3)

The method of manufacturing the semiconductor structure according to claim 3, wherein an extending direction of the lines in the first pattern obliquely intersects a line crossing a closest one of the plurality of second trenches in adjacent rows.

### Claim 9 (depends on 3)

The method of manufacturing the semiconductor structure according to claim 3, wherein:
a depth of one of the plurality of first trenches is greater than a depth of one of the plurality of second trenches, and
a width of one of the plurality of first trenches is smaller than a width of one of the plurality of second trenches.

### Claim 10 (depends on 1)

The method of manufacturing the semiconductor structure according to claim 1, wherein the array of lines in the first pattern are arranged in parallel and spaced apart.

### Claim 11

A semiconductor structure, comprising:
a substrate; and
a second pattern disposed on the substrate, wherein the second pattern is formed by a method comprising:
disposing a plurality of first trenches on the substrate;
forming a first pattern, wherein the first pattern comprises an array of lines each disposed between two adjacent ones of the plurality of first trenches;
forming a first dielectric layer, wherein the first dielectric layer covers at least sidewalls of the array of lines of the first pattern; and
segmenting the first pattern to form the second pattern, wherein forming the first dielectric layer covering at least the sidewalls of the first pattern further comprises:
forming the first dielectric layer on the sidewalls of the array of lines of the first pattern and bottom surfaces of the plurality of first trenches, and
removing the first dielectric layer from the bottom surfaces of the plurality of first trenches, and wherein after forming the first dielectric layer covering the sidewalls of the first pattern and before segmenting the first pattern, the method further comprises:
forming a third dielectric layer in the plurality of first trenches, wherein the third dielectric layer fills the plurality of first trenches.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein:
a width of the first pattern is less than or equal to 20 nm, and
a distance between two adjacent lines in the first pattern is less than or equal to 30 nm.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, wherein segmenting the first pattern to form the second pattern further comprises:
dividing, with a plurality of second trenches, each of in the array of the first pattern into a plurality of elements in the second pattern; and
filling a second dielectric layer in the plurality of second trenches.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the first dielectric layer does not cover sidewalls of each element of the second pattern adjacent to the plurality of second trenches.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein a maximum dimension of one of the plurality of second trenches in a plane parallel to a top surface of the substrate is less than 15 nm.

### Claim 16 (depends on 13)

The semiconductor structure of claim 13, wherein a material of the third dielectric layer is different from a material of the second dielectric layer, and wherein a viscosity of the second dielectric layer is lower than a viscosity of the third dielectric layer.

### Claim 17 (depends on 13)

The semiconductor structure of claim 13, wherein the first dielectric layer is present between adjacent elements in the second pattern, and wherein the first dielectric layer present between the adjacent elements is integrated with the first dielectric layer on sidewalls of each element in the second pattern adjacent to the plurality of first trenches.

### Claim 18 (depends on 13)

The semiconductor structure of claim 13, wherein:
a material of the third dielectric layer is different from a material of the first dielectric layer,
the material of the third dielectric layer is a same as a material of the second dielectric layer.

### Claim 19 (depends on 13)

The semiconductor structure of claim 13, wherein:
a depth of one of the plurality of first trenches is greater than a depth of one of the plurality of second trenches, and
a width of one of the plurality of first trenches is smaller than a width of one of the plurality of second trenches.