# US 12,009,249 B2 · Methods for etching a semiconductor structure and for conditioning a processing reactor

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- Number: US 12,009,249 B2
- Document ID: US12009249B2
- Status: Granted
- Kind: B2
- Application number: 17/969,424
- Filed: 2022-10-19
- Published: 2023-02-16
- Granted: 2024-06-11
- Earliest claimed: 2021-05-13
- Assignees: GlobalWafers Co., Ltd.
- Applicants: GlobalWafers Co., Ltd.
- Inventors: Gang Wang
- Web page: https://patentgrep.com/patent/US12009249B2

## CPC

- C23C 16/0236: {by etching with a reactive gas}
- H10P 72/7616: {characterised by a coating, a hardness or a material}
- C23C 16/24: Deposition of silicon only
- C23C 16/56: After-treatment
- H01J 37/32477: {characterised by the means for protecting vessels or internal parts, e.g. coatings}
- H01J 37/32715: {Workpiece holder}
- H10P 50/242: {of Group IV materials}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/28: of insulating materials
- H10P 50/283: {by chemical means}
- H10P 72/7611: {characterised by edge profile or support profile}
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)

## Abstract

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

## Claims

### Claim 1

A method for etching semiconductor structures in a processing reactor comprising a susceptor which supports a semiconductor structure within a recess of the susceptor, the method comprising:
depositing a first polycrystalline silicon surface layer on the susceptor at a temperature of less than 1150° C.;
loading a first semiconductor structure onto the susceptor having the first polycrystalline silicon surface layer disposed thereon, the first semiconductor structure being disposed within the recess;
contacting the first semiconductor structure with an etchant to etch the semiconductor structure, the first semiconductor structure that is etched being the first semiconductor structure loaded onto the susceptor after the first polycrystalline silicon surface layer is deposited on the susceptor;
removing the first semiconductor structure from the susceptor after the first semiconductor structure has been etched;
contacting the susceptor with a stripping etchant to strip the first polycrystalline silicon surface layer from the susceptor;
depositing a second polycrystalline silicon surface layer on the susceptor at a temperature of less than 1150° C.;
loading a second semiconductor structure onto the susceptor having the second polycrystalline silicon surface layer disposed thereon, the first and second semiconductor structures being semiconductor structures that are consecutively loaded onto the susceptor; and
contacting the second semiconductor structure with the etchant to etch the second semiconductor structure.

### Claim 2 (depends on 1)

The method as set forth in claim 1 wherein the first polycrystalline silicon surface layer and the second polycrystalline silicon surface layer are each deposited by introducing trichlorosilane into the processing reactor.

### Claim 3 (depends on 1)

The method as set forth in claim 1 wherein the first polycrystalline silicon surface layer and the second polycrystalline silicon surface layer are each deposited on the susceptor at a temperature less than 1100° C.

### Claim 4 (depends on 1)

The method as set forth in claim 1 wherein, prior to depositing the first polycrystalline silicon surface layer on the susceptor, the susceptor is contacted with a stripping etchant to strip a previously deposited polycrystalline silicon surface layer from the susceptor.

### Claim 5 (depends on 1)

The method as set forth in claim 1 wherein the first and second semiconductor structures are each a silicon-on-insulator structure having a handle structure, a silicon top layer and a dielectric layer disposed between the handle structure and the silicon top layer.

### Claim 6 (depends on 1)

The method as set forth in claim 1 wherein the first polycrystalline silicon surface layer and the second polycrystalline silicon surface layer each has a thickness of at least 2 μm.

### Claim 7 (depends on 1)

The method as set forth in claim 1 wherein the susceptor is made of silicon carbide.

### Claim 8 (depends on 1)

The method as set forth in claim 1 wherein the susceptor is made of opaque graphite coated with silicon carbide.

### Claim 9 (depends on 1)

The method as set forth in claim 1 wherein the first polycrystalline silicon surface layer and the second polycrystalline silicon surface layer are each deposited by contacting the susceptor with trichlorosilane at a temperature of 900° C. to 1050° C.