# US 12,009,223 B2 · Semiconductor structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,223 B2 - Document ID: US12009223B2 - Status: Granted - Kind: B2 - Application number: 17/445,391 - Filed: 2021-08-18 - Published: 2022-01-20 - Granted: 2024-06-11 - Earliest claimed: 2020-07-16 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Zhongming Liu; Jia Fang - Web page: https://patentgrep.com/patent/US12009223B2 ## CPC - H10P 50/266: {by vapour etching only} - H10B 12/00: Dynamic random access memory [DRAM] devices - H10B 12/482: {Bit lines} - H10P 50/269: {pre- or post-treatments, e.g. anti-corrosion processes} - H10P 50/691: {for Group IV materials or Group III-V materials} - H10P 50/71: {using masks for conductive or resistive materials} - H10W 20/01: {Manufacture or treatment} - H10W 20/031: {of conductive parts of the interconnections} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/43: Layouts of interconnections - H10B 12/485: {Bit line contacts} - H10P 14/6308: {of Group IV semiconductors} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor structure includes: a substrate with a groove structure formed therein is provided; a laminated structure is formed on the substrate, which includes a first conductive material layer, a second conductive material layer and an insulating material layer from bottom up, and the first conductive material layer fills the groove structure and covers the surface of the substrate; the insulating material layer, the second conductive material layer and the first conductive material layer are sequentially etched to form a bit line structure, in which a process of etching the first conductive material layer includes a first etching stage and a second etching stage, such that a bottom width of the first pattern structure located in the groove structure is not smaller than that of the first pattern structure located outside the groove structure. ## Claims ### Claim 1 A method for manufacturing a semiconductor structure, comprising: providing a substrate, a groove structure being forming in the substrate; forming a laminated structure on the substrate, the laminated structure comprising a first conductive material layer, a second conductive material layer and an insulating material layer from bottom up, wherein the first conductive material layer fills the groove structure and covers a surface of the substrate; and etching the insulating material layer, the second conductive material layer and the first conductive material layer sequentially to form an insulating layer, a second conductive layer, and a first conductive layer, respectively, the insulating layer, the second conductive layer and the first conductive layer jointly forming a first pattern structure; wherein a process of etching the first conductive material layer comprises a first etching stage and a second etching stage, wherein in the first etching stage, a first etching gas is used for etching the first conductive material layer until an upper surface of the substrate is exposed; and in the second etching stage, a second etching gas is used for etching the first conductive material layer, wherein the second etching stage comprises a first preset time period and a second preset time period, within the first preset time period, etching the first conductive material layer with the second etching gas containing hydrogen bromide and chlorine till a bottom of the groove structure is exposed; within the second preset time period, stopping introducing the second etching gas, and oxygen is introduced to oxidize the first conductive material layer, to form an oxide layer on the surface of the first conductive material layer; wherein a thickness of the oxide layer on the surface of the first conductive material layer in the groove structure is smaller than that of the oxide layer on the surface of the first conductive material layer outside the groove structure; and the oxide layer is removed to form the first pattern structure; and wherein, a bottom width of the first pattern structure located in the groove structure is greater than a width of the first pattern structure located outside the groove structure. ### Claim 2 (depends on 1) The method for manufacturing the semiconductor structure of claim 1, wherein said etching the insulating material layer, the second conductive material layer and the first conductive material layer sequentially comprises: forming a first hard mask layer on the upper surface of the insulating material layer, wherein the first pattern structure is defined by the first hard mask layer; etching the insulating material layer until the second conductive material layer is exposed by using the first hard mask layer as a mask to form the insulating layer; removing the first hard mask layer; etching the second conductive material layer until the first conductive material layer is exposed by using the insulating layer as a mask, and transferring the first target pattern to the second conductive material layer to form the second conductive layer; and etching the first conductive material layer in stages by using the insulating layer as a mask, wherein the upper surface of the substrate is exposed to form the first pattern structure after the first etching stage is finished, and the first pattern structure is formed in the groove structure after the second etching stage is finished. ### Claim 3 (depends on 1) The method for manufacturing the semiconductor structure of claim 1, wherein said etching the first conductive material layer in the second etching stage comprises: etching the first conductive material layer with the second etching gas containing hydrogen bromide and chlorine, and synchronously introducing oxygen to oxidize the first conductive material layer, therefore the first pattern structure is formed in the groove structure, the oxide layer is formed on the surface of the first conductive layer of the first pattern structure; wherein, a thickness of the oxide layer on the surface of the first conductive material layer in the groove structure is smaller than that of the oxide layer on the surface of the first conductive material layer outside the groove structure; and removing the oxide layer. ### Claim 4 (depends on 1) The method for manufacturing the semiconductor structure of claim 1, wherein a volume ratio of hydrogen bromide to oxygen is in a range of about (100-500):(10-50). ### Claim 5 (depends on 4) The method for manufacturing the semiconductor structure of claim 4, wherein the second etching gas further comprises argon and helium; and a flow rate of hydrogen bromide ranges from about 100 SCCM to about 500 SCCM, a flow rate of chlorine ranges from about 15 SCCM to about 35 SCCM, a flow rate of oxygen ranges from about 10 SCCM to about 50 SCCM, a flow rate of argon ranges from about 400 SCCM to about 600 SCCM, and a flow rate of helium ranges from about 300 SCCM to about 500 SCCM. ### Claim 6 (depends on 5) The method for manufacturing the semiconductor structure of claim 5, wherein a duration of the second etching stage is about 35-45 s. ### Claim 7 (depends on 1) The method for manufacturing the semiconductor structure of claim 1, wherein an etching ability of the first etching gas is stronger than that of the second etching gas. ### Claim 8 (depends on 7) The method for manufacturing the semiconductor structure of claim 7, wherein the first etching gas comprises chlorine, nitrogen, argon, and helium; and a flow rate of chlorine ranges from about 80 SCCM to about 120 SCCM, a flow rate of nitrogen ranges from about 60 SCCM to about 80 SCCM, a flow rate of argon ranges from about 40 SCCM to about 60 SCCM, and a flow rate of helium ranges from about 300 SCCM to about 500 SCCM. ### Claim 9 (depends on 8) The method for manufacturing the semiconductor structure of claim 8, wherein a duration of the first etching phase is about 12-18 s. ### Claim 10 (depends on 1) The method for manufacturing the semiconductor structure of claim 1, wherein said forming the groove structure in the substrate comprises: forming a dielectric layer on the surface of the substrate; forming a second hard mask layer on the surface of the dielectric layer, and the groove structure is defined by the second hard mask layer; and etching the dielectric layer and the substrate to form the groove structure by using the second hard mask layer as a mask. ### Claim 11 (depends on 1) The method for manufacturing the semiconductor structure of claim 1, wherein the first conductive material layer comprises a polysilicon material layer. ### Claim 12 (depends on 11) The method for manufacturing the semiconductor structure of claim 11, wherein said forming the second conductive material layer comprises: forming a metal barrier material layer covering the upper surface of the polysilicon material layer; and forming a metal material layer covering the upper surface of the metal barrier material layer, the metal barrier material layer and the metal material layer jointly forming the second conductive material layer.