# US 12,009,222 B2 · Method for forming semiconductor device structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,222 B2 - Document ID: US12009222B2 - Status: Granted - Kind: B2 - Application number: 17/556,032 - Filed: 2021-12-20 - Published: 2022-04-14 - Granted: 2024-06-11 - Earliest claimed: 2017-09-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yu-Chen Wei; Chun-Chieh Chan; Chun-Jui Chu; Jen-Chieh Lai; Shih-Ho Lin - Web page: https://patentgrep.com/patent/US12009222B2 ## CPC - H10P 52/403: {of conductive or resistive materials} - H10D 64/011: {of electrodes ohmically coupled to a semiconductor} - H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10P 50/71: {using masks for conductive or resistive materials} - H10P 70/277: {the processing being a planarisation of conductive layers} - H10P 72/0412: {using mainly scrubbing means, e.g. brushes} - H10P 72/0414: {using mainly spraying means, e.g. nozzles} - H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures. ## Claims ### Claim 1 A method for forming a semiconductor device structure, comprising: forming a first layer over a substrate; forming a stop layer over the first layer; forming a second layer over the stop layer, wherein the second layer is in direct contact with the stop layer; partially removing the second layer; performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures comprise the stop layer and the upper portion of the first layer remaining after the etching process; and removing the protrusion structures. ### Claim 2 (depends on 1) The method for forming the semiconductor device structure as claimed in claim 1, wherein the removing of the protrusion structures comprises: performing a first planarization process of the first layer. ### Claim 3 (depends on 2) The method for forming the semiconductor device structure as claimed in claim 2, wherein the partially removing of the second layer comprises: performing a second planarization process until the stop layer is exposed. ### Claim 4 (depends on 3) The method for forming the semiconductor device structure as claimed in claim 3, wherein the first planarization process uses a first polishing solution, the second planarization process uses a second polishing solution, and a first abrasive material concentration of the first polishing solution is different from a second abrasive material concentration of the second polishing solution. ### Claim 5 (depends on 4) The method for forming the semiconductor device structure as claimed in claim 4, wherein the first abrasive material concentration of the first polishing solution is less than the second abrasive material concentration of the second polishing solution. ### Claim 6 (depends on 3) The method for forming the semiconductor device structure as claimed in claim 3, wherein the second planarization process uses a polishing solution, and a portion of the polishing solution remains on or in the stop layer and forms residues after the second planarization process. ### Claim 7 (depends on 6) The method for forming the semiconductor device structure as claimed in claim 6, whereby the residues, the stop layer under the residues, and the upper portion of the first layer under the residues together form the protrusion structures. ### Claim 8 (depends on 3) The method for forming the semiconductor device structure as claimed in claim 3, wherein the first planarization process comprises a first chemical mechanical polishing process, and the second planarization process comprises a second chemical mechanical polishing process, the first planarization process uses a first polishing pad to polish the first layer, the second planarization process uses a second polishing pad to polish the second layer, and the first polishing pad is softer than the second polishing pad. ### Claim 9 A method for forming a semiconductor device structure, comprising: providing a first layer; forming a second layer over the first layer, wherein the second layer is made of a semiconductor material; performing a first planarization process to remove an upper portion of the second layer, wherein the first planarization process uses an abrasive material, and a portion of the abrasive material remains on the first layer and forms residues after the first planarization process; removing the residues, wherein the removing of the residues comprises: performing a first cleaning process using a first cleaning solution; and performing a second cleaning process using a second cleaning solution, wherein the first cleaning solution is different from the second cleaning solution, the second cleaning solution comprises a first chelating agent, the second cleaning solution is an acid solution, and the first chelating agent comprises citric acid, oxalic ligand acid, ethylenediamine tetraacetic acid, or etidronic acid; performing an etching process to partially remove an upper portion of the first layer; and performing a second planarization process of the first layer. ### Claim 10 (depends on 9) The method for forming the semiconductor device structure as claimed in claim 9, wherein the first cleaning solution is an alkaline solution. ### Claim 11 (depends on 10) The method for forming the semiconductor device structure as claimed in claim 10, wherein the alkaline solution is a weak alkaline solution. ### Claim 12 (depends on 11) The method for forming the semiconductor device structure as claimed in claim 11, wherein the alkaline solution comprises NH4OH. ### Claim 13 (depends on 9) The method for forming the semiconductor device structure as claimed in claim 9, wherein the second cleaning process uses a brush, the brush is soaked in a third cleaning solution before the second cleaning process, and the third cleaning solution comprises a second chelating agent. ### Claim 14 (depends on 13) The method for forming the semiconductor device structure as claimed in claim 13, wherein the second chelating agent comprises citric acid, oxalic ligand acid, ethylenediamine tetraacetic acid, or etidronic acid. ### Claim 15 (depends on 9) The method for forming the semiconductor device structure as claimed in claim 9, wherein the etching process further removes the second layer remaining over the first layer after the first planarization process. ### Claim 16 A method for forming a semiconductor device structure, comprising: forming a first layer over a substrate, wherein the substrate comprises a base portion and a fin portion over the base portion, the first layer covers the fin portion and the base portion, and the first layer wraps around the fin portion; forming a second layer over the first layer; performing a first planarization process to remove a portion of the second layer; performing an etching process to partially remove an upper portion of the first layer; performing a second planarization process of the first layer; and after performing the second planarization process of the first layer, partially removing a first lower portion of the first layer. ### Claim 17 (depends on 16) The method for forming the semiconductor device structure as claimed in claim 16, further comprising: forming a gate dielectric layer over the base portion and the fin portion before forming the first layer over the substrate, wherein the first layer is formed over the gate dielectric layer. ### Claim 18 (depends on 16) The method for forming the semiconductor device structure as claimed in claim 16, wherein a second lower portion of the first layer remaining after the partially removing of the first lower portion of the first layer has a strip shape in a top view of the first layer. ### Claim 19 (depends on 18) The method for forming the semiconductor device structure as claimed in claim 18, further comprising: forming a spacer over a sidewall of the second lower portion of the first layer. ### Claim 20 (depends on 19) The method for forming the semiconductor device structure as claimed in claim 19, further comprising: forming a dielectric layer over the substrate and surrounding the spacer and the second lower portion of the first layer.