# US 12,009,216 B2 · Methods of forming silicide contact in field-effect transistors

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- Number: US 12,009,216 B2
- Document ID: US12009216B2
- Status: Granted
- Kind: B2
- Application number: 18/358,152
- Filed: 2023-07-25
- Published: 2023-11-16
- Granted: 2024-06-11
- Earliest claimed: 2018-10-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Hsiung Lin; Shih-Cheng Chen; Chih-Hao Wang; Jung-Hung Chang; Jui-Chien Huang
- Web page: https://patentgrep.com/patent/US12009216B2

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0196: {by modifying properties of the inner spacers}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/509: {characterised by the material of the inner spacers}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

## Claims

### Claim 1

A method, comprising:
providing a workpiece comprising a gate structure over a semiconductor fin that protrudes from a substrate;
forming a dielectric structure extending along sidewalls of the gate structure and the semiconductor fin;
etching back the semiconductor fin to form a first recess;
removing a first portion of the dielectric structure to laterally enlarge the first recess;
forming a source/drain (S/D) feature in the enlarged first recess;
after the forming of the S/D feature, removing a second portion of the dielectric structure to form a second recess;
forming a silicide layer in the second recess and on the S/D feature; and
after the forming of the silicide layer, forming an etch stop layer on the silicide layer and a dielectric layer on the etch stop layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the dielectric structure comprises:
conformally depositing a first dielectric material layer over the workpiece; and
depositing a second dielectric material layer over the workpiece to fill spaces between portions of the first dielectric material layer, a composition of the first dielectric material layer is different than a composition of the second dielectric material layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first dielectric material layer comprises a portion extending along a sidewall surface of the semiconductor fin, wherein the removing of the first portion of the dielectric structure comprises performing an etching process to remove the portion of the first dielectric material layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the etching process implements an etchant including hydrofluoric acid, ammonia, or a combination thereof.

### Claim 5 (depends on 2)

The method of claim 2, wherein the removing of the second portion of the dielectric structure comprises performing an etching process to selectively remove the second dielectric material layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising: after the forming of the etch stop layer and the dielectric layer, replacing the gate structure with a gate stack including a high-K dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
after the forming of the etch stop layer and the dielectric layer, forming a source/drain contact extending through the etch stop layer and the dielectric layer to directly contact the silicide layer.

### Claim 8

A method, comprising:
receiving a workpiece comprising a dummy gate structure engaging a semiconductor fin protruding from a substrate, the dummy gate structure extending lengthwise along a first direction;
recessing the semiconductor fin to form a source/drain recess;
enlarging the source/drain recess along the first direction;
forming a source/drain feature in the enlarged source/drain recess;
forming a silicide layer extending along a sidewall surface and a top surface of the source/drain feature;
after the forming of the silicide layer, replacing the dummy gate structure with a metal gate stack.

### Claim 9 (depends on 8)

The method of claim 8, wherein the semiconductor fin comprises a vertical stack of alternating channel layers and sacrificial layers.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
after the enlarging of the source/drain recess along the first direction, selectively recessing the sacrificial layers along a second direction to form inner spacer recesses, the second direction is substantially perpendicular to the first direction; and
forming inner spacer features in the inner spacer recesses.

### Claim 11 (depends on 10)

The method of claim 10, wherein the replacing of the dummy gate structure with the metal gate stack comprises:
after the forming of the silicide layer, depositing a contact etch-stop layer (CESL) over the silicide layer;
forming an interlayer dielectric (ILD) layer over the CESL;
removing the dummy gate structure to from a gate trench;
removing the sacrificial layers to from openings; and
forming the metal gate stack in the gate trench and the openings to wrap around each of the channel layers.

### Claim 12 (depends on 8)

The method of claim 8, wherein the workpiece further comprises a dielectric fin disposed adjacent to the semiconductor fin along the first direction, and the method further comprises:
before the recessing of the semiconductor fin to form the source/drain recess, forming a first dielectric layer over the workpiece, the first dielectric layer comprises a first portion extending along a sidewall surface of the semiconductor fin and a second portion extending along a sidewall surface of the dielectric fin; and
forming a second dielectric layer between the first and second portions of the first dielectric layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the enlarging of the source/drain recess along the first direction comprises removing the first portion of the first dielectric layer.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
before the forming of the silicide layer, selectively removing the second dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
after the selectively removing of the second dielectric layer, selectively removing the second portion of the first dielectric layer.

### Claim 16

A method, comprising:
forming a semiconductor fin protruding from a substrate;
forming a source/drain feature in and over a source/drain region of the semiconductor fin;
forming a silicide layer extending along a sidewall surface and a top surface of the source/drain feature;
conformally forming a contact etch stop layer, the contact etch stop layer comprises a first portion extending along a sidewall surface of the silicide layer and a second portion on a top surface of the source/drain feature; and
forming a source/drain contact extending through the second portion of the contact etch stop layer to directly contact the silicide layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming a dielectric fin adjacent to the semiconductor fin;
comfortably depositing a first dielectric layer over the dielectric fin and the semiconductor fin; and
forming a second dielectric layer over the first dielectric layer, wherein the first portion of the contact etch stop layer is disposed between the silicide layer and the dielectric fin.

### Claim 18 (depends on 17)

The method of claim 17, wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the forming of the source/drain feature comprises:
removing the source/drain region of the semiconductor fin and a portion of the first dielectric layer that extends along the semiconductor fin to form a source/drain recess; and
performing an epitaxial growth process to form the source/drain feature in the source/drain recess.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
before the forming of the silicide layer, selectively removing the second dielectric layer.