# US 12,009,215 B2 · Semiconductor device structure with silicide layer

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- Number: US 12,009,215 B2
- Document ID: US12009215B2
- Status: Granted
- Kind: B2
- Application number: 18/305,074
- Filed: 2023-04-21
- Published: 2023-08-17
- Granted: 2024-06-11
- Earliest claimed: 2018-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Hsiung Lin; Jung-Hung Chang; Shih-Cheng Chen; Kuo-Cheng Chiang; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12009215B2

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate having a base portion and a fin portion over the base portion;
an epitaxial structure over the fin portion;
a dielectric fin over the base portion; and
a silicide layer between the dielectric fin and the epitaxial structure, wherein a void is between the silicide layer and the dielectric fin.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a width of the void increases toward the base portion.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a distance between the void and the epitaxial structure decreases toward the base portion.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the silicide layer wraps around the epitaxial structure.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a contact structure over the silicide layer and the dielectric fin.

### Claim 6 (depends on 5)

The semiconductor device structure as claimed in claim 5, wherein the contact structure is partially between the silicide layer and the dielectric fin.

### Claim 7 (depends on 5)

The semiconductor device structure as claimed in claim 5, wherein a lower portion of the silicide layer is not covered by the contact structure.

### Claim 8 (depends on 7)

The semiconductor device structure as claimed in claim 7, wherein the void is surrounded by the silicide layer, the contact structure, and the dielectric fin.

### Claim 9 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a metal layer covering the silicide layer and the dielectric fin, wherein the void is in the metal layer.

### Claim 10

A semiconductor device structure, comprising:
a substrate having a base portion and a fin portion over the base portion;
an epitaxial structure over the fin portion;
a dielectric fin over the base portion, wherein the dielectric fin is spaced apart from the epitaxial structure; and
a silicide layer wrapping around the epitaxial structure, wherein a first lower portion of the silicide layer is between the epitaxial structure and the base portion.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the silicide layer exposes a second lower portion of a lower surface of the epitaxial structure.

### Claim 12 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the silicide layer has an upper portion, the upper portion is higher than the dielectric fin, and the upper portion is thicker than the first lower portion.

### Claim 13 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
a spacer layer over a first sidewall of the dielectric fin, wherein the first sidewall faces the fin portion of the substrate, and the spacer layer is lower than the epitaxial structure.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the spacer layer exposes an upper portion of the first sidewall of the dielectric fin.

### Claim 15 (depends on 14)

The semiconductor device structure as claimed in claim 14, wherein the dielectric fin has a second sidewall opposite to the first sidewall, the spacer layer covers the second sidewall, and a first top surface of the spacer layer over the second sidewall is substantially level with a second top surface of the dielectric fin.

### Claim 16

A semiconductor device structure, comprising:
a substrate having a base portion and a fin portion over the base portion;
an epitaxial structure over the fin portion;
a liner layer over a sidewall of the fin portion;
a dielectric fin over the base portion, wherein the dielectric fin is spaced apart from the epitaxial structure; and
a silicide layer wrapping around the epitaxial structure, wherein a thickness of the silicide layer decreases toward the liner layer.

### Claim 17 (depends on 16)

The semiconductor device structure as claimed in claim 16, wherein a bottom portion of the silicide layer is in direct contact with the liner layer.

### Claim 18 (depends on 16)

The semiconductor device structure as claimed in claim 16, wherein the liner layer conformally covers the fin portion and the base portion.

### Claim 19 (depends on 16)

The semiconductor device structure as claimed in claim 16, further comprising:
a dielectric layer between the liner layer and the dielectric fin.

### Claim 20 (depends on 19)

The semiconductor device structure as claimed in claim 19, wherein the dielectric layer wraps around a lower portion of the dielectric fin.