# US 12,009,214 B2 · Gate electrodes with notches and methods for forming the same

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- Number: US 12,009,214 B2
- Document ID: US12009214B2
- Status: Granted
- Kind: B2
- Application number: 17/814,691
- Filed: 2022-07-25
- Published: 2022-11-10
- Granted: 2024-06-11
- Earliest claimed: 2012-04-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Min-Feng Kao; Szu-Ying Chen; Dun-Nian Yaung; Jen-Cheng Liu; Tzu-Hsuan Hsu; Feng-Chi Hung
- Web page: https://patentgrep.com/patent/US12009214B2

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10P 30/212: {Through-implantation}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

## Claims

### Claim 1

A device, comprising:
a semiconductor substrate comprising an active region;
a transistor comprising:
a gate dielectric over the semiconductor substrate;
a gate electrode over the gate dielectric, wherein the gate electrode comprises a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness, and wherein the gate electrode comprises a notch;
a first source/drain region and a second source/drain region on opposite sides of the gate electrode, wherein the first source/drain region and the second source/drain region extend into the semiconductor substrate; and
a device isolation ring encircling both of the first source/drain region and the second source/drain region, wherein the device isolation ring comprises:
a first portion having a first lengthwise direction parallel to a channel-length direction of the transistor, wherein the gate electrode comprises a first edge parallel to the first lengthwise direction, and wherein the first edge overlaps the first portion of the device isolation ring; and
a second portion parallel to the first portion of the device isolation ring and overlapped by the notch, wherein the gate electrode crosses over, and extends to opposite sides of, the second portion of the device isolation ring, and wherein first opposing edges of the notch are flush with second opposing edges of the second portion of the device isolation ring.

### Claim 2 (depends on 1)

The device of claim 1, wherein the gate electrode further comprises a step comprising:
a first top surface;
a second top surface lower than the first top surface and extending to the first edge; and
a sidewall connecting the first top surface to the second top surface.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first portion of the device isolation ring comprises a first sidewall and a second sidewall parallel to the first lengthwise direction, and wherein in a top view of the device, the first edge of the gate electrode is laterally between the first sidewall and the second sidewall.

### Claim 4 (depends on 1)

The device of claim 1, further comprising a well region directly underlying the gate dielectric, the first source/drain region, and the second source/drain region, wherein the well region and the device isolation ring are of a same conductivity type.

### Claim 5 (depends on 1)

The device of claim 1, wherein in a top view of the device, the device isolation ring is a full ring.

### Claim 6 (depends on 1)

The device of claim 1, wherein the device comprises an image sensor die.

### Claim 7

A device, comprising:
a semiconductor substrate comprising an active region;
a device isolation region in the semiconductor substrate, wherein an entirety of the device isolation region is a semiconductor region;
a well region extending into the active region, wherein the device isolation region and the well region are of a same conductivity type; and
a transistor comprising:
a gate dielectric comprising a portion overlapping and physically contacting the device isolation region; and
a gate electrode over the gate dielectric, wherein the gate electrode comprises a notch at a top surface of the gate electrode, and wherein the notch overlaps the portion of the gate dielectric, wherein the gate electrode crosses over a portion of the device isolation region, wherein a portion of the gate electrode crossing over the device isolation region comprises an additional notch, the additional notch comprising an inner edge and an outer edge vertically aligned to respective edges of the portion of the device isolation region.

### Claim 8 (depends on 7)

The device of claim 7, further comprising a source region and a drain region in the well region, with both of the source region and the drain region comprising edges joining to the device isolation region.

### Claim 9 (depends on 8)

The device of claim 8, wherein the source region and the drain region have an opposite conductivity type than the device isolation region.

### Claim 10 (depends on 8)

The device of claim 8, wherein the gate electrode comprises a step comprising:
a first top surface of the gate electrode;
a second top surface of the gate electrode extending directly over a portion of the device isolation region; and
a sidewall of the gate electrode, wherein the sidewall connects the first top surface to the second top surface, and wherein the second top surface and the sidewall collectively form the notch.

### Claim 11 (depends on 10)

The device of claim 10, wherein the sidewall of the gate electrode is parallel to a lengthwise direction of the portion of the device isolation region.

### Claim 12 (depends on 11)

The device of claim 11, wherein the sidewall of the gate electrode forming the notch overlaps an additional sidewall of the portion of the device isolation region.

### Claim 13 (depends on 7)

The device of claim 7, wherein the device comprises an image sensor die.

### Claim 14

A device, comprising:
a semiconductor substrate;
a device isolation region extending into the semiconductor substrate, wherein the device isolation region forms a ring comprising an outer sidewall forming an outer ring, and an inner sidewall forming an inner ring, and wherein an entirety of the device isolation region is a semiconductor region;
a gate dielectric over the semiconductor substrate;
a gate electrode over the gate dielectric, wherein in a top view of the device, the gate electrode comprises:
an end portion overlapping the inner ring, and the end portion is spaced apart from the outer ring, and wherein in the top view of the device, the end portion comprises an end edge parallel to respective portions of the inner ring and the outer ring, and the end edge is between the respective portions of the inner ring and the outer ring in the top view; and
an additional portion crossing over the device isolation region, wherein in the top view of the device, the gate electrode comprises a first part inside the inner ring, and a second portion outside the outer ring; and
a source region and a drain region in a portion of the semiconductor substrate encircled by the ring.

### Claim 15 (depends on 14)

The device of claim 14, wherein the end portion of the gate electrode comprises a notch, with a top surface of the gate electrode being at a bottom of the notch, wherein the notch overlaps the device isolation region, and wherein an inner edge of the notch overlaps a portion of the inner ring.

### Claim 16 (depends on 14)

The device of claim 14, wherein the device isolation region has a first conductivity type opposing to a second conductivity type of the source region and the drain region.

### Claim 17 (depends on 14)

The device of claim 14, wherein the additional portion further comprises an additional notch.

### Claim 18 (depends on 17)

The device of claim 17, wherein the additional notch comprises additional edges overlapping some portions of the inner ring and the outer ring.

### Claim 19 (depends on 14)

The device of claim 14, wherein the device comprises an image sensor die.

### Claim 20 (depends on 14)

The device of claim 14, wherein the gate dielectric is over and contacts the device isolation region.