# US 12,009,213 B2 · Semiconductor power device and method for producing same

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- Number: US 12,009,213 B2
- Document ID: US12009213B2
- Status: Granted
- Kind: B2
- Application number: 17/591,384
- Filed: 2022-02-02
- Published: 2022-05-19
- Granted: 2024-06-11
- Earliest claimed: 2011-02-02
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Yuki Nakano
- Web page: https://patentgrep.com/patent/US12009213B2

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 64/01366: {the semiconductor being silicon carbide}
- H10D 8/051: {of Schottky diodes}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 8/60: Schottky-barrier diodes
- H10D 12/031: {of IGBTs}
- H10D 30/01: Manufacture or treatment
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8303: {Diamond}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D 64/01364: {the semiconductor being diamond, semiconducting diamond-like carbon or graphene}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10P 14/6312: {of Group III-V semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

## Claims

### Claim 1

A wide bandgap semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
a gate trench disposed over the semiconductor substrate;
a gate insulating film disposed along a side of the gate trench and a bottom surface of the gate trench, and partly covering a surface of the semiconductor substrate;
a gate electrode disposed so as to be buried in the gate trench;
an interlayer insulating film disposed so as to cover the gate electrode and the gate insulating film;
an intermediate stacked portion disposed over the semiconductor substrate and the interlayer insulating film;
a metal layer disposed on or over the intermediate stacked portion;
a first source region having the first conductivity type disposed near the side of the gate trench from a surface of the semiconductor substrate;
a first body region having a second conductivity type disposed under the first source region, the first body region disposed along the side of the gate trench
a body contact region electrically connected to the first body region in a cross sectional view; and
a diode region disposed lower than the first body region in a cross sectional view, wherein
a pn-diode having a pn-junction is disposed in the diode region such that the pn-junction is lower than the bottom surface of the gate trench
a width of the diode region is wider than a width of the first body region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the side of the gate trench is connected to the bottom surface of the gate trench via a curved surface in a cross-sectional view.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein
the gate trench extends continuously to at least a first direction continuously.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein
the semiconductor substrate is made of silicon carbide.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a plurality of gate trenches disposed at constant intervals.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein
the metal layer includes an Aluminum layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein
the intermediate stacked portion has a layer including Titanium.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein
a side surface of the gate insulating film is flush with a side of the interlayer insulating film.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein
the intermediate stacked portion has a substantially uniform thickness.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein
a length of the body contact region is about 1.6 um in a cross sectional view.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein
a length of the first body region is about 7.2 um in a cross sectional view.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein
a length of the first source region is about 5.7 μm in a cross sectional view.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein
an interval between the first body region and a second body region next to the first body region is about 2.8 um.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein
a thickness of the intermediate stacked portion is between 5000 Å and 10000 Å.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein
a thickness of the intermediate stacked portion is between 200 nm and 500 nm.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, wherein
a thickness of the metal layer is between 1 μm and 5 μm.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate withstand voltage holding region disposed so as to extend to a backside direction of the semiconductor substrate from the bottom surface of the gate trench.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein
the gate withstand voltage holding region having a thickness at least 0.8 μm is formed from the bottom surface of the gate trench to a backside of the semiconductor substrate.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, wherein
a width of the diode region is greater than or equal to 4 μm in a cross sectional view.

### Claim 20

A wide bandgap semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
a gate trench disposed over the semiconductor substrate;
a gate insulating film disposed along a side and bottom of the gate trench, and at least partially covering a surface of the semiconductor substrate;
a gate electrode disposed in the gate trench;
an interlayer insulating film disposed over the gate electrode and the gate insulating film;
an intermediate stacked portion disposed over the semiconductor substrate and the interlayer insulating film;
a metal layer disposed on or over the intermediate stacked portion;
a first source region having the first conductivity type formed from a surface of the semiconductor substrate along the side of the gate trench;
a first body region having a second conductivity type disposed under the first source region and along the side of the gate trench; and
a diode region disposed lower than the first body region in a cross-sectional view, wherein
a pn-diode having a pn-junction is disposed in the diode region such that the pn-junction is lower than the surface of the gate trench, and
a width of the diode region is wider than a width of the first body region.