# US 12,009,209 B2 · Process for preparing a support for a semiconductor structure

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- Number: US 12,009,209 B2
- Document ID: US12009209B2
- Status: Granted
- Kind: B2
- Application number: 17/938,427
- Filed: 2022-10-06
- Published: 2023-02-02
- Granted: 2024-06-11
- Earliest claimed: 2017-06-30
- Assignees: Soitec
- Applicants: Soitec
- Inventors: Young-Pil Kim
- Web page: https://patentgrep.com/patent/US12009209B2

## CPC

- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10P 90/1918: {including charge trapping layers, e.g. polycrystalline materials}
- C23C 16/24: Deposition of silicon only
- C23C 16/26: Deposition of carbon only
- C23C 16/4404: {Coatings or surface treatment on the inside of the reaction chamber or on parts thereof}
- C23C 16/4405: {Cleaning of reactor or parts inside the reactor by using reactive gases}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)

## Abstract

A process for preparing a support comprises the placing of a substrate on a susceptor in a chamber of a deposition system, the susceptor having an exposed surface not covered by the substrate; the flowing of a precursor containing carbon in the chamber at a deposition temperature so as to form at least one layer on an exposed face of the substrate, while at the same time depositing species of carbon and of silicon on the exposed surface of the susceptor. The process also comprises, directly after the removal of the substrate from the chamber, a first etch step consisting of the flowing of an etch gas in the chamber at a first etching temperature not higher than the deposition temperature so as to eliminate at least some of the species of carbon and silicon deposited on the susceptor.

## Claims

### Claim 1

A charge trapping layer for a semiconductor structure support, comprising:
at least one polycrystalline charge trapping material; and
at least one polycrystalline interlayer directly adjacent to the charge trapping material, the at least one polycrystalline interlayer comprising an alloy of silicon and carbon,
wherein a lattice parameter of the at least one polycrystalline charge trapping material is greater than a lattice parameter of the at least one polycrystalline interlayer.

### Claim 2 (depends on 1)

The charge trapping layer of claim 1, wherein a grain size of the at least one polycrystalline charge trapping material is between 100 nanometers (nm) and 1000 nm.

### Claim 3 (depends on 1)

The charge trapping layer of claim 1, wherein the at least one polycrystalline interlayer comprises silicon carbide or carbon-doped silicon.

### Claim 4 (depends on 1)

The charge trapping layer of claim 1, wherein the at least one polycrystalline charge trapping material is rich in carbon or nitrogen.

### Claim 5 (depends on 1)

The charge trapping layer of claim 1, comprising an alternating stack of the at least one polycrystalline charge trapping material and the at least one polycrystalline interlayer.

### Claim 6 (depends on 5)

The charge trapping layer of claim 5, wherein the alternating stack comprises between one and ten polycrystalline interlayers.

### Claim 7

A support for a semiconductor structure, comprising:
a base substrate; and
a charge trapping layer on the base substrate, the charge trapping layer comprising an alternating stack of at least one polycrystalline charge trapping material and at least one polycrystalline interlayer,
wherein the at least one polycrystalline interlayer comprises an alloy of silicon and carbon and at least one of silicon oxide and silicon nitride.

### Claim 8 (depends on 7)

The support for a semiconductor structure of claim 7, wherein the charge trapping layer has a thickness greater than 2 microns.

### Claim 9 (depends on 7)

The support for a semiconductor structure of claim 7, wherein a thickness of the at least one polycrystalline interlayer is less than 10 nm.

### Claim 10 (depends on 7)

The support for a semiconductor structure of claim 7, wherein a thickness of the at least one polycrystalline charge trapping material is between 0.2 microns (μm) and 2.5 μm.

### Claim 11 (depends on 7)

The support for a semiconductor structure of claim 7, further comprising a silicon dioxide insulating layer directly on the base substrate, the silicon dioxide insulating layer disposed between the base substrate and the charge trapping layer.

### Claim 12 (depends on 11)

The support for a semiconductor structure of claim 11, wherein the silicon dioxide insulating layer has a thickness greater than 20 nm.

### Claim 13 (depends on 7)

The support for a semiconductor structure of claim 7, wherein the charge trapping layer has a resistivity greater than 1000 ohmcentimeters (ohm·cm).

### Claim 14

A semiconductor structure, comprising:
a charge trapping layer on a base substrate, the charge trapping layer comprising an alternating stack of at least one polycrystalline charge trapping material and at least one polycrystalline interlayer, wherein the at least one polycrystalline interlayer comprises an alloy of silicon and carbon;
a silicon dioxide insulating layer on the base substrate, the silicon dioxide insulating layer disposed between the base substrate and the charge trapping layer; and
a useful layer over the charge trapping layer.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, further comprising an insulating layer on the charge trapping layer, the insulating layer disposed between the charge trapping layer and the useful layer.

### Claim 16 (depends on 14)

The semiconductor structure of claim 14, wherein the semiconductor structure comprises a surface acoustic wave device or a bulk acoustic wave device.

### Claim 17 (depends on 14)

The semiconductor structure of claim 14, wherein the useful layer comprises a piezoelectric material.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein the piezoelectric material comprises lithium tantalate.