# US 12,009,202 B2 · Using a self-assembly layer to facilitate selective formation of an etching stop layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,202 B2 - Document ID: US12009202B2 - Status: Granted - Kind: B2 - Application number: 17/379,161 - Filed: 2021-07-19 - Published: 2021-11-11 - Granted: 2024-06-11 - Earliest claimed: 2018-06-27 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Shao-Kuan Lee; Hsin-Yen Huang; Yung-Hsu Wu; Cheng-Chin Lee; Hai-Ching Chen; Shau-Lin Shue - Web page: https://patentgrep.com/patent/US12009202B2 ## CPC - H10P 14/6506: {Formation of intermediate materials} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 84/853: {comprising FinFETs} - H10P 14/61: using masks - H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD} - H10P 14/6938: {the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/0693: {by forming self-aligned vias} - H10W 20/075: {of multilayered thin functional dielectric layers} - H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/42: Vias, e.g. via plugs - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening. ## Claims ### Claim 1 A method, comprising: providing a structure that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component; selectively forming a self-assembly layer directly on an upper surface of the first conductive component; selectively forming a first dielectric layer over the first ILD; forming a second ILD over the first conductive component and over the first ILD; etching an opening in the second ILD, wherein the opening is at least partially aligned with the first conductive component, wherein the first dielectric layer protects portions of the first ILD located therebelow from being etched; and filling the opening with a conductive material to form a second conductive component in the opening. ### Claim 2 (depends on 1) The method of claim 1, wherein the forming the first dielectric layer comprises performing a deposition process using precursors, and wherein during the forming of the first dielectric layer, the self-assembly layer prevents the precursors from being formed on the first conductive component. ### Claim 3 (depends on 1) The method of claim 1, wherein the forming of the self-assembly layer comprises depositing the self-assembly layer that includes a head group and a tail group, wherein the head group comprises phosphorous, sulfur, or silicon, and wherein the tail group comprises an organic material. ### Claim 4 (depends on 3) The method of claim 3, further comprising: removing the tail group by a thermal process, by a plasma treatment, or by an application of a chemical. ### Claim 5 (depends on 1) The method of claim 1, wherein the etching is configured such that the second ILD has a substantially greater etching rate than the first dielectric layer. ### Claim 6 (depends on 1) The method of claim 1, further comprising: forming an etching stop layer over the first conductive component and over the first ILD, wherein the second ILD is formed over the etching stop layer. ### Claim 7 (depends on 1) The method of claim 1, further comprising: before the forming of the first dielectric layer, forming a second dielectric layer on the first ILD, wherein the self-assembly layer prevents the second dielectric layer from being formed on the first conductive component, and wherein the first dielectric layer is formed on the second dielectric layer. ### Claim 8 (depends on 7) The method of claim 7, wherein the forming the second dielectric layer comprises forming the second dielectric layer with a lower dielectric constant than the first dielectric layer. ### Claim 9 (depends on 7) The method of claim 7, wherein the forming the second dielectric layer comprises forming the second dielectric layer with a greater thickness than the first dielectric layer. ### Claim 10 A method, comprising: forming a first layer over a first conductive component, wherein the first conductive component is surrounded laterally by a first interlayer dielectric (ILD), and wherein the first layer includes a head group that has an affinity with the first conductive component but not with the first ILD; selectively depositing a first dielectric layer over the first ILD; forming a second ILD over the first layer and over the first dielectric layer; etching an opening in the second ILD, wherein the opening at least partially exposes an upper surface of the first conductive component and partially exposes an upper surface of the first dielectric layer; and forming a second conductive component in the opening. ### Claim 11 (depends on 10) The method of claim 10, wherein the forming the first layer comprises forming the first layer that includes a tail group that is organized into a plurality of strands that are separate from one another and that each extend at least partially upwards. ### Claim 12 (depends on 11) The method of claim 11, wherein the head group comprises phosphorous, sulfur, or silicon, and wherein the tail group comprises an organic material, and wherein the method further comprises: after the first dielectric layer has been selectively deposited, removing the tail group by a thermal process, by a plasma treatment, or by an application of a chemical. ### Claim 13 (depends on 10) The method of claim 10, wherein the first layer is a self-assembled layer and is formed directly on an upper surface of the first conductive component. ### Claim 14 (depends on 10) The method of claim 10, wherein the opening is etched without completely exposing the first conductive component. ### Claim 15 (depends on 10) The method of claim 10, further comprising: after the first dielectric layer has been deposited but before the second ILD has been formed, forming an etching-stop layer over the first layer and over the first dielectric layer, wherein the second ILD is formed over the etching-stop layer. ### Claim 16 (depends on 10) The method of claim 10, further comprising: before the second ILD is formed, depositing a second dielectric layer over the first dielectric layer, wherein the first dielectric layer and the second dielectric layer have different material compositions, and wherein the second ILD is formed over the second dielectric layer. ### Claim 17 A method, comprising: forming a first conductive component in a first interlayer dielectric (ILD); forming a first layer directly on an upper surface of the first conductive component, wherein the first layer includes a head group and a tail group, wherein the head group has an affinity with the first conductive component but not with the first ILD, and wherein the tail group includes a plurality of strands that are horizontally separated from one another and that each extend at least partially upwards; selectively depositing a first dielectric layer over the first ILD; forming a second ILD over the first layer and over the first dielectric layer; performing an etching process to form an opening that vertically extends through the second ILD and the first layer, wherein the first dielectric layer has a substantially lower etching rate than the second ILD and the first layer during the etching process; and filling the opening with a second conductive component. ### Claim 18 (depends on 17) The method of claim 17, further comprising: removing the tail group of the first layer after the first dielectric layer has been selectively deposited, wherein the removing the tail group is performed using a thermal process, using a plasma treatment, or using a chemical. ### Claim 19 (depends on 17) The method of claim 17, further comprising: before the second ILD is formed, depositing a second dielectric layer over the first dielectric layer, wherein the first dielectric layer and the second dielectric layer have different material compositions, and wherein the second ILD is formed over the second dielectric layer. ### Claim 20 (depends on 17) The method of claim 17, further comprising: before the second ILD is formed, forming an etching-stop layer over the first layer and over the first dielectric layer, wherein the second ILD is formed over the etching-stop layer.