# US 12,009,055 B2 · Far end driver for memory clock > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,055 B2 - Document ID: US12009055B2 - Status: Granted - Kind: B2 - Application number: 17/571,670 - Filed: 2022-01-10 - Published: 2022-10-20 - Granted: 2024-06-11 - Earliest claimed: 2021-04-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Atul Katoch - Web page: https://patentgrep.com/patent/US12009055B2 ## CPC - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 8/10: Decoders - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 11/417: for memory cells of the field-effect type - G11C 11/418: Address circuits - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices. ## Claims ### Claim 1 A memory device, comprising: a plurality of memory cells in a plurality of rows in a memory array; a first memory clock driver disposed on a first side of the plurality of rows of the memory array, and a second memory clock driver disposed on a second side, opposite to the first side of the plurality of rows of the memory array, wherein the first and second memory clock drivers are configured to transmit a word line clock signal, in response to a master clock signal, to activate a row of memory cells in the plurality of rows of the memory array using the first and second memory clock drivers, and a row selection circuit configured to select a row of memory cells in the plurality of rows of the memory array using an address of the row of memory cells, wherein the row selection circuit includes: a first logical gate configured to receive the address; a second logical gate coupled to an output of the first logic gate and configured to receive the word line clock signal; and a third logical gate coupled between the output of the second logical gate and the row of memory cells. ### Claim 2 (depends on 1) The memory device of claim 1, wherein: the first memory clock driver comprises a first decoder; and the second memory clock driver comprises a second decoder. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the first memory clock driver is configured to receive the master clock signal and transmit the master clock signal to the second memory clock driver. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the first memory clock driver and the second memory clock driver are both configured to receive the master clock signal concurrently. ### Claim 5 (depends on 2) The memory device of claim 2, wherein: the first memory clock driver and the second memory clock driver are configured to receive an address corresponding to a row of memory cells in the plurality of rows, the address being decoded by the first decoder and the second decoder to correspond to the row of memory cells in the plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit the word line clock signal, in response to a master clock signal, to activate the row of memory cells in the plurality of rows corresponding to the address through the conductive line coupled between the first and second memory clock drivers. ### Claim 6 (depends on 5) The memory device of claim 5, wherein: the first logical gate is a logical AND gate; the second logical gate is a logical NAND gate; and the third logical gate is a logical NOT gate. ### Claim 7 (depends on 2) The memory device of claim 2, wherein each of the first and second decoders comprise a circuit corresponding to each row of memory cells in the plurality of rows comprising: a logical NAND gate configured to receive two bits of the address as inputs; and a logical NOR gate electrically coupled to an output of the logical NAND gate as a first input and the master clock signal as a second input, wherein the output of the logical NOR gate is the word line clock signal to activate the row of memory cells in the plurality of rows. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the NOR gate is comprised of: a first transistor having a first terminal electrically coupled to a voltage source and a gate terminal electrically coupled to the output of the logical NAND gate; a second transistor having a first terminal electrically coupled to a second terminal of the first transistor and a gate terminal electrically coupled to the clock signal; and a third transistor having a first terminal electrically coupled to a second terminal of the second transistor and the conductive line carrying the word line clock signal as an output of the decoder, a gate terminal electrically coupled to the clock signal, and a second terminal electrically coupled to an electrical ground. ### Claim 9 (depends on 2) The memory device of claim 2, wherein each of the first and second decoders comprise a circuit corresponding to each row of memory cells in the plurality of rows comprising a logical NOR gate electrically coupled to the master clock signal as a first input and a bit of the address as a second input, wherein the output of the logical NOR gate is the word line clock signal to activate the row of memory cells in the plurality of rows. ### Claim 10 (depends on 1) The memory device of claim 1, further comprising a local I/O, the local I/O being configured to transmit the master clock signal to one or more of the first and second memory clock drivers. ### Claim 11 (depends on 1) The memory device of claim 1, further comprising a clock signal generator, the clock signal generator electrically coupled to one or more of the first and second memory clock drivers, wherein the clock signal generator transmits the master clock signal to the one or more first and second memory clock drivers. ### Claim 12 A method for operating a memory device comprising the steps of: decoding an address of a row of memory cells in a memory array at first memory clock driver; and activating the row of memory cells in the memory array corresponding to the address by the first memory clock driver and a second memory clock driver, the second memory clock driver oriented on an opposite side of the row of memory cells in the memory array from the first memory clock driver, wherein at least one of the first and second memory clock drivers includes a logical gate configured to receive the address and a master clock signal and to generate a word line clock signal that activates the row of memory cells. ### Claim 13 (depends on 12) The method of claim 12, further comprising the first memory clock driver transmitting the master clock signal to the second memory clock driver. ### Claim 14 (depends on 12) The method of claim 12, wherein the master clock signal is received by the first memory clock driver and the second memory clock driver concurrently. ### Claim 15 (depends on 12) The method of claim 12, further comprising receiving a row select address at a row select circuit, wherein the row select circuit selects a row of memory cells corresponding to the row select address. ### Claim 16 (depends on 12) The method of claim 12, wherein the first memory clock driver transmits a decoded address corresponding to the row of memory cells to the second memory clock driver, the second memory clock driver activating the row of memory cells corresponding to the decoded address. ### Claim 17 (depends on 12) The method of claim 12, further comprising the second memory clock driver: receiving the address corresponding to a row of memory cells; decoding the address corresponding to the row of memory cells; activating the row of memory cells corresponding to the address. ### Claim 18 A memory clock driver circuit coupled to an array of memory cells, the memory clock driver circuit comprising: a first memory clock driver disposed on a first side of a plurality of rows of memory cells, and a second memory clock driver disposed on a second side, opposite to the first side of the plurality of rows, wherein the first and second memory clock drivers are configured to transmit a word line clock signal, in response to a master clock signal, to activate a row of memory cells in the plurality of rows through a conductive line coupled between the first and second memory clock drivers, and wherein the first memory clock driver includes different components than the second memory clock drivers such that the second memory clock driver is configured to receive the master clock signal through the first memory clock driver. ### Claim 19 (depends on 18) The memory clock driver circuit of claim 18, wherein: the first memory clock driver and the second memory clock driver are configured to receive an address corresponding to a row of memory cells in the plurality of rows, the address being decoded by the first memory clock driver and the second memory clock driver to correspond to the row of memory cells in the plurality of rows, and the first memory clock driver and the second memory clock driver are configured to transmit the word line clock signal, in response to the master clock signal, to activate the row of memory cells in the plurality of rows corresponding to the address through the conductive line coupled between the first and second memory clock drivers. ### Claim 20 (depends on 18) The memory clock driver circuit of claim 18, wherein at least one of the first and second memory clock drivers includes a logical gate configured to receive an address of a row of memory cells in the plurality of row and a master clock signal and to generate a word line clock signal that activates the row of memory cells.