# US 12,009,052 B2 · Apparatuses including multiple read modes and methods for same

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- Number: US 12,009,052 B2
- Document ID: US12009052B2
- Status: Granted
- Kind: B2
- Application number: 17/814,790
- Filed: 2022-07-25
- Published: 2023-02-16
- Granted: 2024-06-11
- Earliest claimed: 2015-09-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Theodore T. Pekny
- Web page: https://patentgrep.com/patent/US12009052B2

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 16/30: Power supply circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

## Claims

### Claim 1

An apparatus comprising:
a charge pump circuit configured to develop a voltage prior to execution of a read command; and
a global word line driver configured to receive the voltage and to drive a plurality of global word lines of a memory prior to execution of the read command.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a memory having a read mode configurable to execute the read command.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the global word line driver is further configured to precharge the plurality of global word lines to the voltage to drive the plurality of global word lines, prior to execution of the read command at the memory.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein, after execution of the read command at the memory in accordance with the read mode, the charge pump circuit is further configured to develop the voltage prior to the execution of another read command at the memory in accordance with read mode.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein, after execution of the read command at the memory in accordance with the read mode, the global word line driver is further configured to precharge the plurality of global word lines prior to the execution of another read command at the memory in accordance with read mode.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the voltage is less than a voltage used by the global word lines during execution of the read command.

### Claim 7 (depends on 2)

The apparatus of claim 2, wherein the read mode is a set feature operation mode that is enabled using a set feature operation.

### Claim 8 (depends on 7)

The apparatus of claim 7, further comprising:
control logic configured to provide to the memory a control signal configured enable a sub-operation of the set feature operation mode.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the sub-operation enabled by the control signal corresponds to the charge pump circuit developing the voltage prior to execution of the read command at the memory.

### Claim 10

A method comprising:
developing a voltage prior to execution of a read command; and
receiving the voltage and driving a plurality of global word lines prior to execution of the read command.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
executing the read command by a read mode of a memory.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
precharging the plurality of global word lines to the voltage to drive the plurality of global word lines, prior to execution of the read command at the memory.

### Claim 13 (depends on 11)

The method of claim 11, further comprising, after execution of the read command at the memory in accordance with the read mode:
developing the voltage prior to the execution of another read command at the memory in accordance with read mode.

### Claim 14 (depends on 12)

The method of claim 12, further comprising, after execution of the read command at the memory in accordance with the read mode:
precharging the plurality of global word lines prior to the execution of another read command at the memory in accordance with read mode.

### Claim 15 (depends on 11)

The method of claim 11, wherein the voltage is less than a voltage used by the global word lines during execution of the read command.

### Claim 16 (depends on 11)

The method of claim 11, wherein the read mode is a set feature operation mode that is enabled using a set feature operation.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
providing to the memory a control signal configured enable a sub-operation of the set feature operation mode.

### Claim 18 (depends on 17)

The method of claim 17, wherein the sub-operation enabled by the control signal corresponds to developing the voltage prior to execution of the read command at the memory.

### Claim 19

An apparatus, comprising:
a charge pump configured to provide a voltage;
a global word line driver configured to receive the voltage from the charge pump and drive a global word line to the voltage prior to execution of a read command; and
a local word line decoder configured to provide the voltage to one or more local word lines.

### Claim 20 (depends on 19)

The apparatus of claim 19, where in the local word line decoder is configured to provide the voltage to the one or more local word lines based at least in part on a row address signal.