# US 12,009,051 B2 · Method of storing data in memories > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,051 B2 - Document ID: US12009051B2 - Status: Granted - Kind: B2 - Application number: 17/747,318 - Filed: 2022-05-18 - Published: 2023-12-28 - Granted: 2024-06-11 - Earliest claimed: 2022-05-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Win-San Khwa; Jui-Jen Wu; Jen-Chieh Liu; Meng-Fan Chang - Web page: https://patentgrep.com/patent/US12009051B2 ## CPC - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/1069: {I/O lines read out arrangements} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1675: {Writing or programming circuits or methods} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state. ## Claims ### Claim 1 A method comprising: reading a characterization bit of a data stored in bit cells, each bit cell having a first state and a second state, wherein reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or wherein the bit cell with the first state has less retention errors than the bit cell with the second state; reading a stored bit in a bit cell through a sense amplifier and through either a first read path or a second read path selected based on the characterization bit; wherein the sense amplifier is configured to generate a sensed bit from the stored bit, the first read path is configured to generate a first output bit from the sensed bit when the first read path is selected, and the second read path is configured to generate a second output bit from the sensed bit when the second read path is selected; and wherein the first output bit generated from the sensed bit in response to the first read path being selected is configured to be a bitwise complement of the second output bit generated from the sensed bit in response to the second read path being selected. ### Claim 2 (depends on 1) The method of claim 1, wherein reading the stored bit in the data comprises: reading the sensed bit at an output of the sense amplifier directly if the characterization bit is a first value, and reading the sensed bit at an output of the sense amplifier through an inverter if the characterization bit is a second value that is different from the first value. ### Claim 3 (depends on 2) The method of claim 2, wherein the characterization bit is a most significant bit. ### Claim 4 (depends on 2) The method of claim 2, wherein the characterization bit is a bit immediately adjacent to a most significant bit. ### Claim 5 (depends on 2) The method of claim 2, wherein the characterization bit is a bit that is separated from a most significant bit by one or more bits. ### Claim 6 An integrated circuit comprising: a memory storage having bit cells, wherein a bit cell has a first state and a second state, wherein either the memory storage is configured to cause the bit cell with the first state being read out with less energy than the bit cell with the second state or configured to cause the bit cell with the first state having less retention errors than the bit cell with the second state; a write path switch configured to have a connection state determined by a characterization bit; a write terminal configured to receive a data of a data set; a write driver having an input configured to receive an input data from the write terminal through either a first write path or a second write path as determined by the connection state of the write path switch, wherein the write driver is operative to write an input bit of the input data into the bit cell as a stored bit; and wherein the input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the characterization bit is a most significant bit. ### Claim 8 (depends on 6) The integrated circuit of claim 6, wherein the characterization bit is a bit immediately adjacent to a most significant bit. ### Claim 9 (depends on 6) The integrated circuit of claim 6, wherein the characterization bit is a bit that is separated from a most significant bit by one or more bits. ### Claim 10 (depends on 6) The integrated circuit of claim 6, wherein the first write path includes an electric conductor connected between the input of the write driver and the write terminal, and the second write path includes an inverter operationally connected between the input of the write driver and the write terminal. ### Claim 11 An integrated circuit comprising: a memory storage having bit cells, wherein a bit cell has a first state and a second state, wherein either the memory storage is configured to cause the bit cell with the first state being read out with less energy than the bit cell with the second state or configured to cause the bit cell with the first state having less retention errors than the bit cell with the second state; a write path switch configured to have a connection state determined by a characterization bit; a write terminal configured to receive a data of a data set; a write driver having an input configured to receive an input data from the write terminal through either a first write path or a second write path as determined by the connection state of the write path switch, wherein the write driver is operative to write an input bit of the input data into the bit cell as a stored bit; wherein the input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal; and a read path switch configured to have a connection state determined by the characterization bit. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the first read path includes an electric conductor connected between an output of the sense amplifier and the read terminal, and the second read path includes an inverter operationally connected between the output of the sense amplifier and the read terminal. ### Claim 13 (depends on 6) The integrated circuit of claim 6, wherein the characterization bit is a most significant bit. ### Claim 14 (depends on 6) The integrated circuit of claim 6, wherein the characterization bit is a bit immediately adjacent to a most significant bit. ### Claim 15 (depends on 6) The integrated circuit of claim 6, wherein the characterization bit is a bit that is separated from a most significant bit by one or more bits. ### Claim 16 (depends on 6) The integrated circuit of claim 6, further comprising: a bit-state indicator latch having an output terminal configured to generate a latch output signal to control the write path switch. ### Claim 17 (depends on 6) The integrated circuit of claim 6, further comprising: a read path switch configured to have a connection state determined by the characterization bit; a sense amplifier configured to detect a stored bit in a bit cell and operable to output a bit read value to a read terminal through either a first read path or a second read path as determined by the connection state of the read path switch; and wherein a first bit value outputted to the read terminal through the first read path is configured to have a same binary value as the stored bit and a second bit value outputted to the read terminal through the second read path is configured to have a complement binary value as the stored bit. ### Claim 18 (depends on 11) The integrated circuit of claim 11, wherein the first read path includes an electric conductor connected between an output of the sense amplifier and the read terminal, and the second read path includes an inverter operationally connected between the output of the sense amplifier and the read terminal. ### Claim 19 (depends on 11) The integrated circuit of claim 11, further comprising: a bit-state indicator latch having an input connected to an output of the sense amplifier. ### Claim 20 (depends on 11) The integrated circuit of claim 11, further comprising: a sense amplifier configured to detect a stored bit in a bit cell and operable to output a bit read value to a read terminal through either a first read path or a second read path as determined by the connection state of the read path switch; and wherein a first bit value outputted to the read terminal through the first read path is configured to have a same binary value as the stored bit and a second bit value outputted to the read terminal through the second read path is configured to have a complement binary value as the stored bit.