# US 12,009,050 B2 · Selective access for grouped memory dies

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- Number: US 12,009,050 B2
- Document ID: US12009050B2
- Status: Granted
- Kind: B2
- Application number: 17/875,960
- Filed: 2022-07-28
- Published: 2023-02-09
- Granted: 2024-06-11
- Earliest claimed: 2021-07-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yang Lu; Kang-Yong Kim
- Web page: https://patentgrep.com/patent/US12009050B2

## CPC

- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/1066: {Output synchronization}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/4401: {for self repair}
- G11C 29/46: Test trigger logic
- G11C 2207/105: Aspects related to pads, pins or terminals
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

## Claims

### Claim 1

An apparatus, comprising:
a plurality of memory dies;
a command/address channel coupled with each memory die of the plurality, wherein each of the memory dies is operable by a same command received over the command/address channel; and
circuitry coupled with the plurality of memory dies and the command/address channel and operable to:
receive, over the command/address channel, a first command enabling a set of commands for a first memory die of the plurality and disabling a first subset of the set of commands for a second memory die of the plurality;
receive, over the command/address channel, a second command indicating one or more operations to perform for the plurality of memory dies, the first subset of commands comprising the second command; and
perform the one or more operations for the first memory die in response to the second command.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the circuitry is further operable to:
restrict the second memory die from performing the one or more operations in response to the second command.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the circuitry is further operable to:
configure the first memory die to operate in a first mode based at least in part on the first command, wherein configuring the first mode comprises enabling the set of commands for the first memory die; and
configure the second memory die to operate in a second mode based at least in part on the first command, wherein configuring the second mode comprises disabling the first subset of commands and enabling a second subset of the set of commands for the second memory die.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the circuitry is further operable to:
configure the second memory die to operate in a third mode based at least in part on the first command, wherein configuring the third mode comprises disabling a third subset of commands of the set of commands and enabling a fourth subset of commands of the set of commands for the second memory die, wherein the third subset of commands is different than the first subset of commands and the fourth subset of commands is different than the second subset of commands.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein:
the second mode comprises a first level of a select die access protocol; and
the third mode comprises a second level of the select die access protocol.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein the circuitry is further operable to:
configures the second memory die to operate in the third mode based at least in part on entering a repair mode or a test mode for the plurality of memory dies.

### Claim 7 (depends on 3)

The apparatus of claim 3, further comprising:
a first register associated with the first memory die and operable to store an identifier of the first memory die and an indication of whether the first memory die is configured to operate in the first mode or the second mode; and
a second register associated with the second memory die and operable to store an identifier of the second memory die and an indication of whether the second memory die is configured to operate in the first mode or the second mode.

### Claim 8 (depends on 3)

The apparatus of claim 3, further comprising:
a register operable to store an indication of a level associated with the second mode and an indication of whether the first mode and the second mode are enabled.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the first command comprises a multipurpose (MPC) command that is associated with synchronization and calibration operations of the plurality of memory dies.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first command comprises a command that is associated with enabling and disabling commands received via the command/address channel for the plurality of memory dies.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the one or more operations comprise a write operation to a register of the apparatus that is associated with the first memory die, a repair operation for the first memory die, or both.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein:
the plurality of memory dies is coupled with a host device and is accessible by a peripheral device coupled with the host device via an interface configured for a Compute Express Link (CXL) protocol; or
the plurality of memory dies is coupled with the peripheral device and is accessible by the host device via the interface.

### Claim 13

An apparatus, comprising:
circuitry operable to:
transmit, over a command/address channel, a first command enabling a set of commands for a first memory die of a plurality of memory dies each coupled with the command/address channel and disabling a first subset of the set of commands for a second memory die of the plurality; and
transmit, over the command/address channel, a second command indicating one or more operations to perform for the plurality of memory dies, the first subset of commands comprising the second command.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the first command further indicates for the first memory die to operate in a first mode in which the set of commands is enabled and indicates for the second memory die to operate in a second mode in which the first subset of commands is disabled and a second subset of the set of commands is enabled.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the circuitry is further operable to:
configure the second memory die to operate in a third mode based at least in part on the first command, wherein configuring the third mode comprises disabling a third subset of commands of the set of commands and enabling a fourth subset of commands of the set of commands for the second memory die, wherein the third subset of commands is different than the first subset of commands and the fourth subset of commands is different than the second subset of commands.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein:
the second mode comprises a first level of a select die access protocol; and
the third mode comprises a second level of the select die access protocol.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the circuitry is further operable to:
configure the second memory die to operate in the third mode based at least in part on entering a repair mode or a test mode for the plurality of memory dies.

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein the first command comprises a multipurpose (MPC) command that is associated with synchronization and calibration operations for the plurality of memory dies.

### Claim 19 (depends on 13)

The apparatus of claim 13, wherein the first command comprises a command that is associated with enabling and disabling commands received via the command/address channel for the plurality of memory dies.

### Claim 20 (depends on 13)

The apparatus of claim 13, wherein the one or more operations comprise a write operation to a register associated with the first memory die, a repair operation for the first memory die, or both.

### Claim 21 (depends on 13)

The apparatus of claim 13, wherein:
the plurality of memory dies is coupled with the apparatus and is accessible by a peripheral device coupled with the apparatus via an interface configured for a Compute Express Link (CXL) protocol; or
the plurality of memory dies is coupled with the peripheral device and is accessible by the apparatus via the interface.

### Claim 22

A method, comprising:
receiving, at a memory device and over a command/address channel coupled with each of a plurality of memory dies, a first command enabling a set of commands for a first memory die of the plurality and disabling a first subset of the set of commands for a second memory die of the plurality, wherein each of the memory dies is operable by a same command received over the command/address channel;
receiving, over the command/address channel, a second command indicating one or more operations to perform for the plurality of memory dies, the first subset of commands comprising the second command; and
performing the one or more operations for the first memory die in response to the second command.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
restricting the second memory die from performing the one or more operations in response to the second command.

### Claim 24 (depends on 22)

The method of claim 22, further comprising:
configuring the first memory die to operate in a first mode based at least in part on the first command, wherein configuring the first mode comprises enabling the set of commands for the first memory die; and
configuring the second memory die to operate in a second mode based at least in part on the first command, wherein configuring the second mode comprises disabling the first subset of commands and enabling a second subset of the set of commands for the second memory die.

### Claim 25 (depends on 24)

The method of claim 24, further comprising:
configuring the second memory die to operate in a third mode based at least in part on the first command, wherein configuring the third mode comprises disabling a third subset of commands of the set of commands and enabling a fourth subset of commands of the set of commands for the second memory die, wherein the third subset of commands is different than the first subset of commands and the fourth subset of commands is different than the second subset of commands.

### Claim 26 (depends on 25)

The method of claim 25, wherein:
the second mode comprises a first level of a select die access protocol; and
the third mode comprises a second level of the select die access protocol.

### Claim 27 (depends on 25)

The method of claim 25, further comprising:
configuring the second memory die to operate in the third mode based at least in part on entering a repair mode or a test mode for the plurality of memory dies.

### Claim 28 (depends on 24)

The method of claim 24, further comprising:
storing, at a first register associated with the first memory die, an identifier of the first memory die and an indication of whether the first memory die is configured to operate in the first mode or the second mode; and
storing, at a second register associated with the second memory die, an identifier of the second memory die and an indication of whether the second memory die is configured to operate in the first mode or the second mode.

### Claim 29 (depends on 24)

The method of claim 24, further comprising:
storing, at a register of the memory device, an indication of a level associated with the second mode and an indication of whether the first mode and the second mode are enabled.

### Claim 30 (depends on 22)

The method of claim 22, wherein the first command comprises a multipurpose (MPC) command that is associated with synchronization and calibration operations of the plurality of memory dies.

### Claim 31 (depends on 22)

The method of claim 22, wherein the first command comprises a command that is associated with enabling and disabling commands received via the command/address channel for the plurality of memory dies.

### Claim 32 (depends on 22)

The method of claim 22, wherein the one or more operations comprise a write operation to a register of the memory device that is associated with the first memory die, a repair operation for the first memory die, or both.

### Claim 33 (depends on 22)

The method of claim 22, wherein:
the plurality of memory dies is coupled with a host device and is accessible by a peripheral device coupled with the host device via an interface configured for a Compute Express Link (CXL) protocol; or
the plurality of memory dies is coupled with the peripheral device and is accessible by the host device via the interface.

### Claim 34

A method, comprising:
transmitting, over a command/address channel coupled with each of a plurality of memory dies, a first command enabling a set of commands for a first memory die of the plurality and disabling a first subset of the set of commands for a second memory die of the plurality; and
transmitting, over the command/address channel, a second command indicating one or more operations to perform for the plurality of memory dies, the first subset of commands comprising the second command.

### Claim 35 (depends on 34)

The method of claim 34, wherein the first command further indicates for the first memory die to operate in a first mode in which the set of commands is enabled and indicates for the second memory die to operate in a second mode in which the first subset of commands is disabled and a second subset of the set of commands is enabled.

### Claim 36 (depends on 35)

The method of claim 35, further comprising:
configuring the second memory die to operate in a third mode based at least in part on the first command, wherein configuring the third mode comprises disabling a third subset of commands of the set of commands and enabling a fourth subset of commands of the set of commands for the second memory die, wherein the third subset of commands is different than the first subset of commands and the fourth subset of commands is different than the second subset of commands.

### Claim 37 (depends on 36)

The method of claim 36, wherein:
the second mode comprises a first level of a select die access protocol; and
the third mode comprises a second level of the select die access protocol.

### Claim 38 (depends on 36)

The method of claim 36, further comprising:
configuring the second memory die to operate in the third mode based at least in part on entering a repair mode or a test mode for the plurality of memory dies.

### Claim 39 (depends on 34)

The method of claim 34, wherein the first command comprises a multipurpose (MPC) command that is associated with synchronization and calibration operations for the plurality of memory dies.

### Claim 40 (depends on 34)

The method of claim 34, wherein the first command comprises a command that is associated with enabling and disabling commands received via the command/address channel for the plurality of memory dies.

### Claim 41

A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
receive, via a command/address channel coupled with each of a plurality of memory dies, a first command enabling a set of commands for a first memory die of the plurality and disabling a first subset of the set of commands for a second memory die of the plurality, wherein each of the memory dies is operable by a same command received over the command/address channel;
receive a second command via the command/address channel indicating one or more operations to perform for the plurality of memory dies, the first subset of commands comprising the second command; and
perform the one or more operations for the first memory die in response to the second command.