# US 12,009,049 B2 · Non-volatile memory with shared data transfer latches > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,049 B2 - Document ID: US12009049B2 - Status: Granted - Kind: B2 - Application number: 17/900,066 - Filed: 2022-08-31 - Published: 2024-02-29 - Granted: 2024-06-11 - Earliest claimed: 2022-08-31 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Hua-Ling Cynthia Hsu; YenLung Li; Siddarth Naga Murty Bassa; Jeongduk Sohn - Web page: https://patentgrep.com/patent/US12009049B2 ## CPC - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1087: {Data input latches} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 7/106: {Data output latches} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 2207/101: Analog or multilevel bus - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. ## Claims ### Claim 1 An apparatus, comprising: a control circuit configured to connect to an array of non-volatile memory cells, the control circuit comprising: a first plurality of data latches configured to connect to non-volatile memory cells of a first plane; a second plurality of data latches configured to connect to non-volatile memory cells of a second plane; and a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a first dynamic data latch connected to the first plurality of data latches and a second dynamic data latch connected to the second plurality of data latches. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein: the first dynamic data latch is configured for transfer of data with the shared data transfer data latch and with the first plurality of data latches; and the second dynamic data latch is configured for transfer of data with the shared data transfer data latch and with the second plurality of data latches. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising: a first local bus connecting the first plurality of data latches; and a second local bus connecting the second plurality of data latches. ### Claim 5 (depends on 4) The apparatus of claim 4, further comprising: a first dynamic data latch connected to the first local bus; and a second dynamic data latch connected to the second local bus. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein each data latch of the first plurality of data latches, the second plurality of data latches and the shared data transfer data latch is a non-volatile data latch. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the first dynamic data latch and second dynamic data latch are volatile latches that require periodic refresh operations to maintain stored data. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein each latch of the first plurality of data latches, the second plurality of data latches and the shared data transfer data latch is larger than the first dynamic data latch and the second dynamic data latch. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein: the first plurality of data latches includes at least five data latches including a first sense data latch configured to store a sensed bit from a first sense amplifier; and the second plurality of data latches includes at least five data latches including a second sense data latch configured to store a sensed bit from a second sense amplifier. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the control circuit is formed on a first die and is configured to connect to the array formed on a second die. ### Claim 11 A method, comprising: transferring first data to a shared data transfer data latch; subsequently transferring the first data to a first data latch of a first plurality of data latches that are connected to non-volatile memory cells of a first plane; transferring second data to the shared data transfer data latch; and subsequently transferring the second data to a second data latch of a second plurality of data latches that are connected to non-volatile memory cells of a second plane. ### Claim 12 (depends on 11) The method of claim 11, further comprising: transferring the first data from the shared data transfer data latch to a first dynamic data latch; and transferring the first data from the first dynamic data latch to the first data latch. ### Claim 13 (depends on 12) The method of claim 12, further comprising: transferring the second data from the shared data transfer data latch to a second dynamic data latch; and transferring the second data from the second dynamic data latch to the second data latch. ### Claim 14 (depends on 13) The method of claim 13, further comprising: refreshing at least one of the first data in the first dynamic data latch and the second data in the second dynamic data latch. ### Claim 15 (depends on 11) The method of claim 11, further comprising: transferring third data from a first sense amplifier to the first data latch; subsequently transferring the third data from the first data latch to the shared data transfer data latch; transferring fourth data from a second sense amplifier to the second data latch; and subsequently transferring the fourth data from the second data latch to the shared data transfer data latch. ### Claim 16 (depends on 15) The method of claim 15, further comprising: transferring the third data from the first data latch to a first dynamic data latch; subsequently transferring the third data from the first dynamic data latch to the shared data transfer data latch; transferring the fourth data from the second data latch to a second dynamic data latch; and subsequently transferring the fourth data from the second dynamic data latch to the shared data transfer data latch. ### Claim 17 (depends on 16) The method of claim 16, further comprising: transferring the third data from the shared data transfer data latch to a memory controller; and transferring the fourth data from the shared data transfer data latch to the memory controller. ### Claim 18 A non-volatile memory device, comprising: a plurality of non-volatile memory cells arranged in a plurality of planes including at least a first plane and a second plane; and a control circuit configured to connect to the plurality of non-volatile memory cells, the control circuit comprising: a first plurality of data latches configured to connect to non-volatile memory cells of a first plane; a second plurality of data latches configured to connect to non-volatile memory cells of a second plane; and means for latching data for transfer to and from the first plurality of data latches and the second plurality of data latches. ### Claim 19 (depends on 18) The non-volatile memory device of claim 18, further comprising: first means for volatile storage of data, the first means for volatile storage of data connected to the first plurality of data latches; and second means for volatile storage of data, the second means for volatile storage of data connected to the second plurality of data latches. ### Claim 20 (depends on 18) The non-volatile memory device of claim 18, wherein the plurality of non-volatile memory cells are formed on a first die and the control circuit is formed on a second die.