# US 12,009,042 B2 · Executing a refresh operation in a memory sub-system

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- Number: US 12,009,042 B2
- Document ID: US12009042B2
- Status: Granted
- Kind: B2
- Application number: 17/980,234
- Filed: 2022-11-03
- Published: 2023-02-23
- Granted: 2024-06-11
- Earliest claimed: 2020-10-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Vamsi Pavan Rayaprolu; Kishore Kumar Muchherla; Ashutosh Malshe; Gianni S. Alsasua; Harish R. Singidi
- Web page: https://patentgrep.com/patent/US12009042B2

## CPC

- G11C 29/42: using error correcting codes [ECC] or parity check
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0882: Page mode
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/32: Serial access; Scan testing
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G06F 2212/1016: Performance improvement
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7206: Reconfiguration of flash memory system
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.

## Claims

### Claim 1

A method comprising:
executing a scan operation to identify a trigger rate associated with a set of memory pages of a data block of a memory device, wherein the trigger rate represents a number of the set of memory pages that fail an error management operation;
comparing the trigger rate to a threshold trigger rate to determine that a condition is satisfied; and
in response to satisfying the condition, executing, by a processing device, a refresh operation on the set of memory pages of the data block.

### Claim 2 (depends on 1)

The method of claim 1, wherein the condition is satisfied when the trigger rate exceeds the threshold trigger rate.

### Claim 3 (depends on 1)

The method of claim 1, wherein the trigger rate represents a ratio of the number of the set of memory pages that fail the error management operation in view of a total number of the set of memory pages.

### Claim 4 (depends on 1)

The method of claim 1, wherein executing the refresh operation further comprises reading data of the set of memory pages of the data block.

### Claim 5 (depends on 4)

The method of claim 4, wherein executing the refresh operation further comprises executing a further error management operation on the data to generate corrected data.

### Claim 6 (depends on 5)

The method of claim 5, wherein executing the refresh operation comprises programming the corrected data to another data block.

### Claim 7 (depends on 1)

The method of claim 1, wherein the threshold trigger rate comprises an adjustable threshold trigger rate.

### Claim 8 (depends on 7)

The method of claim 7, wherein the adjustable threshold trigger rate is adjusted in view of a workload type associated with the data block.

### Claim 9 (depends on 8)

The method of claim 8, wherein the workload type comprises one of a uniform workload type or a non-uniform workload type.

### Claim 10 (depends on 7)

The method of claim 7, wherein the adjustable threshold trigger rate is adjusted in view of a soft correction process.

### Claim 11

A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
executing a scan operation to identify a trigger rate associated with a set of memory pages of a data block of the memory device, wherein the trigger rate represents a number of the set of memory pages that fail an error management operation;
comparing the trigger rate to a threshold trigger rate to determine that a condition is satisfied; and
in response to satisfying the condition, executing a refresh operation on the set of memory pages of the data block.

### Claim 12 (depends on 11)

The system of claim 11, wherein the condition is satisfied when the trigger rate exceeds the threshold trigger rate.

### Claim 13 (depends on 11)

The system of claim 11, wherein the trigger rate represents a ratio of the number of the set of memory pages that fail the error management operation in view of a total number of the set of memory pages.

### Claim 14 (depends on 11)

The system of claim 11, wherein executing the refresh operation further comprises reading data of the set of memory pages of the data block.

### Claim 15 (depends on 14)

The system of claim 14, wherein executing the refresh operation further comprises executing a further error management operation on the data to generate corrected data.

### Claim 16 (depends on 15)

The system of claim 15, wherein executing the refresh operation comprises programming the corrected data to another data block.

### Claim 17 (depends on 11)

The system of claim 11, wherein the threshold trigger rate comprises an adjustable threshold trigger rate.

### Claim 18 (depends on 17)

The system of claim 17, wherein the adjustable threshold trigger rate is adjusted in view of a workload type associated with the data block.

### Claim 19 (depends on 18)

The system of claim 18, wherein the workload type comprises one of a uniform workload type or a non-uniform workload type.

### Claim 20 (depends on 17)

The system of claim 17, wherein the adjustable threshold trigger rate is adjusted in view of a soft correction process.
