# US 12,009,036 B2 · NAND flash memory device and method of reducing program disturb thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,036 B2 - Document ID: US12009036B2 - Status: Granted - Kind: B2 - Application number: 17/529,567 - Filed: 2021-11-18 - Published: 2023-05-04 - Granted: 2024-06-11 - Earliest claimed: 2021-10-30 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Hongtao Liu; Dejia Huang; Wenzhe Wei; Ying Huang - Web page: https://patentgrep.com/patent/US12009036B2 ## CPC - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell. ## Claims ### Claim 1 A memory device, comprising: memory strings each comprising a drain select gate (DSG) transistor and memory cells; and a peripheral circuit coupled to the memory strings and configured to, in a program/verify cycle: program a target memory cell of the memory cells in a select memory string of the memory strings; after programming the target memory cell, verify the target memory cell using one or more verify voltages comprising an initial verify voltage; compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result; and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the target memory cell, wherein to control the DSG transistor, the peripheral circuit is further configured to, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, turn on the DSG transistor in the unselect memory string in an interval between an end of programming and a start of verifying the target memory cell, and wherein the initial verify voltage is a maximum voltage of the one or more verify voltages. ### Claim 2 (depends on 1) The memory device of claim 1, wherein to control the DSG transistor, the peripheral circuit is configured to, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being higher than the threshold verify voltage, turn off the DSG transistor in the unselect memory string between programming and verifying the target memory cell. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the initial verify voltage in the program/verify cycle is lower than another initial verify voltage in a later program/verify cycle; and the peripheral circuit is further configured to, in response to the comparing result indicative of the initial verify voltage being higher than the threshold verify voltage in the program/verify cycle, in the later program/verify cycle, turn off the DSG transistor between programming and verifying the target memory cell without comparing the another initial verify voltage with the threshold verify voltage. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the threshold verify voltage is determined based, at least in part, on a sequence number of the program/verify cycle among a plurality of program/verify cycles. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the peripheral circuit is further configured to: turn off the DSG transistor in the unselect memory string when programming the target memory cell; and turn off the DSG transistor in the unselect memory string when verifying the target memory cell. ### Claim 6 (depends on 1) The memory device of claim 1, further comprising word lines each coupled to the memory cells in the select and unselect memory strings that are in a same respective row, wherein the peripheral circuit comprises a word line driver configured to, when verifying the target memory cell: sequentially apply the one or more verify voltages, starting from the initial verify voltage, to a select word line coupled to the target memory cell; and apply a pass voltage to an unselect word line coupled to another memory cell of the memory cells in the select memory string. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the pass voltage is higher than the initial verify voltage. ### Claim 8 (depends on 6) The memory device of claim 6, wherein the threshold verify voltage is determined based, at least in part, on the pass voltage. ### Claim 9 (depends on 6) The memory device of claim 6, wherein the word line driver is further configured to: in response to the comparing result indicative of the initial verify voltage being higher than the threshold verify voltage, apply a first voltage to the select word line between programming and verifying the target memory cell, to turn off a memory cell in the unselect memory string and that is coupled to the select word line; and in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, apply a second voltage to the select word line in the interval between programming and verifying the target memory cell, to turn on the memory cell in the unselect memory string. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the peripheral circuit is configured to turn on the DSG transistor after verifying the target memory cell. ### Claim 11 A memory system, comprising: a memory device configured to store data and comprising: memory strings each comprising a drain select gate (DSG) transistor and memory cells; and a peripheral circuit coupled to the memory strings and configured to, in a program/verify cycle: program a target memory cell of the memory cells in a select memory string of the memory strings; after programming the target memory cell, verify the target memory cell using one or more verify voltages comprising an initial verify voltage; compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result; and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the target memory cell, wherein to control the DSG transistor, the peripheral circuit is further configured to, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, turn on the DSG transistor in the unselect memory string in an interval between an end of programming and a start of verifying the target memory cell, wherein the initial verify voltage is a maximum voltage of the one or more verify voltages; and a memory controller coupled to the memory device and configured to control operations of the memory strings through the peripheral circuit. ### Claim 12 A method for operating a memory device, the memory device comprising memory strings each comprising a drain select gate (DSG) transistor and memory cells, the method comprising, in a program/verify cycle: programming a target memory cell of the memory cells in a select memory string of the memory strings; after programming the target memory cell, verifying the target memory cell using one or more verify voltages comprising an initial verify voltage; comparing the initial verify voltage with a threshold verify voltage so as to obtain a comparing result; and controlling, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the target memory cell, wherein controlling the DSG transistor comprises, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, turning on the DSG transistor in the unselect memory string in an interval between an end of programming and a start of verifying the target memory cell, and wherein the initial verify voltage is a maximum voltage of the one or more verify voltages. ### Claim 13 (depends on 12) The method of claim 12, wherein controlling the DSG transistor comprises, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being higher than the threshold verify voltage, turning off the DSG transistor in the unselect memory string between programming and verifying the target memory cell. ### Claim 14 (depends on 12) The method of claim 12, wherein: the memory device further comprises word lines each coupled to the memory cells in the select and unselect memory strings that are in a same respective row; and verifying the target memory cell comprises: sequentially applying the one or more verify voltages, starting from the initial verify voltage, to a select word line coupled to the target memory cell; and applying a pass voltage to an unselect word line coupled to another memory cell of the memory cells in the select memory string. ### Claim 15 (depends on 14) The method of claim 14, wherein the threshold verify voltage is determined based, at least in part, on the pass voltage. ### Claim 16 (depends on 14) The method of claim 14, further comprising: in response to the comparing result indicative of the initial verify voltage being higher than the threshold verify voltage, applying a first voltage to the select word line between programming and verifying the target memory cell to turn off a memory cell in the unselect memory string and that is coupled to the select word line; and in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, applying a second voltage to the select word line in the interval between programming and verifying the target memory cell to turn on the memory cell in the unselect memory string.