# US 12,009,035 B2 · Apparatus for controlling NAND flash memory device and method for controlling same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,035 B2 - Document ID: US12009035B2 - Status: Granted - Kind: B2 - Application number: 17/766,028 - Filed: 2020-10-05 - Published: 2022-10-27 - Granted: 2024-06-11 - Earliest claimed: 2019-10-04 - Assignees: LG Innotek Co., Ltd. - Applicants: LG Innotek Co., Ltd. - Inventors: Sang Hoon Shin; Hyoung Ki Nam - Web page: https://patentgrep.com/patent/US12009035B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 16/30: Power supply circuits - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A control apparatus for a NAND flash memory device according to an embodiment includes a NAND flash memory; a controller configured to generate a command signal to program, read, and erase data in the NAND flash memory; and an auxiliary power circuit configured to maintain power for operating the memory and the controller during a first time from a first time point when a voltage of a supply power is less than a preset voltage, wherein the controller is configured to block the command signal during the first time, and wherein power supplied to the memory is blocked for at least a second time from a second time point after the first time. ## Claims ### Claim 1 A power supply device, comprising: a memory; a converter connected the memory and converting an input voltage of a supply power to supply an output voltage to the memory; an input voltage detector connected to the converter and detecting a level of the input voltage; a controller connected to the memory and controlling access to the memory based on the level of the input voltage; and an auxiliary power unit connected to the memory and the controller and supplying a driving voltage to the memory and the controller for a preset time, wherein the controller is configured to: generate a command signal to program, read, and erase data in the memory when the level of the input voltage is greater than or equal to a first level, control the auxiliary power unit so that the driving voltage for driving the memory and the controller is maintained for a first time period from a first time point at which the level of the input voltage becomes less than or equal to a second level, block the command signal for the first time period, and block power from being supplied to the memory regardless of a level of the input voltage for at least a second time period from a second time point after the first time period has elapsed, and wherein when the level of the input voltage is greater than or equal to the first level before the second time period elapses from the second time point, the controller blocks power from being supplied to the memory. ### Claim 2 (depends on 1) The power supply device of claim 1, wherein when the first time point is a program operation time (tPROG) or an erase operation time (tBERS) of the memory, the auxiliary power unit supplies the driving voltage for completing the program operation or erase operation of the memory. ### Claim 3 (depends on 2) The power supply device of claim 2, wherein when the first time point is in an electronic movement based on the program operation time (tPROG) or the erase operation time (tBERS) of the memory, the auxiliary power unit is configured to supply the driving voltage for completing the program operation or erase operation of the memory. ### Claim 4 (depends on 1) The power supply device of claim 1, wherein the first time period is a time until a program operation or an erase operation being performed in the memory before the first time point is completed. ### Claim 5 (depends on 1) The control apparatus of claim 1, further comprising: a power management IC (PMIC) connected to the converter and supplying the driving voltage to the memory and the controller. ### Claim 6 (depends on 5) The control apparatus of claim 5, wherein the auxiliary power unit is disposed between the PMIC and the memory. ### Claim 7 (depends on 5) The power supply device of claim 5, wherein the controller is configured to control the PMIC so that power is supplied to the memory after the power supply is blocked for the at least second time period. ### Claim 8 (depends on 5) The power supply device of claim 5, wherein the auxiliary power unit is connected to a power input terminal of the PMIC. ### Claim 9 (depends on 8) The power supply device of claim 8, wherein the input voltage detector is configured to detect a voltage level of an input terminal of the auxiliary power unit. ### Claim 10 (depends on 8) The power supply device of claim 8, further comprising: a detection signal transmitter configured to transmit the voltage level detected through the input voltage detector to the controller. ### Claim 11 (depends on 10) The power supply device of claim 10, wherein the detection signal transmitter includes a first resistor, a second resistor, a third resistor, and a transistor. ### Claim 12 (depends on 11) The power supply device of claim 11, wherein one end of the first resistor is connected to an output terminal of the input voltage detector, wherein the other end of the first resistor is connected to one end of the third resistor and a base of the transistor, wherein one end of the second resistor is connected to a power terminal of the supply power, wherein the other end of the second resistor is connected to a collector of the transistor and a signal input terminal of the controller, wherein one end of the third resistor is connected to the one end of the first resistor and the base of the transistor; and wherein the other end of the third resistor is connected to an emitter and a ground terminal of the transistor. ### Claim 13 (depends on 5) The power supply device of claim 5, further comprising: a regulator disposed between the supply power and the PMIC; wherein the auxiliary power unit is disposed between the regulator and the PMIC. ### Claim 14 (depends on 1) The power supply device of claim 1, wherein the controller is configured to ignore a voltage change of the supply power in an ACC ON state. ### Claim 15 (depends on 1) The power supply device of claim 1, wherein when the level of the input voltage is greater than or equal to the first level for a third time period from a third time point after the second time has elapsed, the controller is configured to supply power to the memory. ### Claim 16 (depends on 1) The power supply device of claim 1, wherein when the level of the input voltage is greater than or equal to the first level while the driving voltage is maintained, the controller is configured to reset the memory. ### Claim 17 (depends on 1) The power supply device of claim 1, wherein when a predetermined time has elapsed from a point in time when ACC OFF is detected, the controller is configured to control an operation of the memory based on a change in the level of the input voltage. ### Claim 18 A method for controlling a NAND flash memory device, comprising: detecting a voltage level of a supply power; when the voltage level is greater than or equal to a first level, generating a command signal to program, read, and erase data in the memory; when the voltage level less than or equal to a second level, stopping access to the memory; supplying a driving voltage by an auxiliary power unit for driving the memory for a first time period from a first time point at which the voltage level becomes less than or equal to the second level; and blocking power from being supplied to the memory regardless of a voltage level of the supply power for at least a second time period from a second time point after the first time period has elapsed, and wherein the stopping of the access comprises: blocking a command signal for controlling the memory, and wherein when the voltage level is greater than or equal to the first level before the second time period elapses from the second time point, the power supplied to the memory is blocked during the second time period. ### Claim 19 (depends on 18) The method of claim 18, wherein the supplying of the driving voltage comprises: supplying the driving voltage for completion of a program operation or an erase operation of the memory when the first time point is the program operation time (tPROG) or the erase operation time (tBERS) of the memory. ### Claim 20 (depends on 19) The method of claim 19, wherein the first time period is a time until the program operation or the erase operation being performed in the memory before the first time point is completed.