# US 12,009,031 B2 · Memory array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,031 B2 - Document ID: US12009031B2 - Status: Granted - Kind: B2 - Application number: 17/888,294 - Filed: 2022-08-15 - Published: 2023-08-24 - Granted: 2024-06-11 - Earliest claimed: 2022-02-18 - Assignees: Shanghai Huahong Grace Semiconductor Manufacturing Corporation - Applicants: Shanghai Huahong Grace Semiconductor Manufacturing Corporation - Inventors: Ning Wang; Kegang Zhang - Web page: https://patentgrep.com/patent/US12009031B2 ## CPC - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory array that includes a plurality of storage cells, a plurality of bit lines, a plurality of memory transistor word lines and a plurality of selection transistor word lines, wherein the storage cells form an array of M rows*N columns; each storage cell includes a selection transistor and a memory transistor connected in series; a source and a gate of each selection transistor are connected, and the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line. ## Claims ### Claim 1 A memory array, wherein the memory array comprises: a plurality of storage cells forming an array of M rows*N columns, each storage cell comprising a selection transistor and a memory transistor connected in series; a plurality of bit lines arranged at intervals along the direction of columns, wherein drains of the memory transistors in the same column are connected to a corresponding bit line; a plurality of memory transistor word lines arranged at intervals along the direction of rows; and a plurality of selection transistor word lines arranged at intervals along the direction of rows, wherein the memory transistor word lines and the selection transistor word lines are arranged alternately, gates of the memory transistors in the same row are connected to a corresponding memory transistor word line, a source and a gate of each selection transistor are connected, the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line, and all storage cells share a well region; erasing, programming and reading of the storage cells are realized by applying certain voltage to the selection transistor word lines connected to the gates of the selection transistors, the memory transistor word lines connected to the gates of the memory transistors and the bit lines connected to the drains of the memory transistors. ### Claim 2 (depends on 1) The memory array according to claim 1, wherein it is defined that the voltage applied to the selection transistor word line is Vwl, the voltage applied to the memory transistor word line is Vwls, the voltage applied to the bit line is Vbl and the voltage applied to the well region is Vbpw; it is defined that Vpos is first positive voltage, Vneg is negative voltage, Vpwr is a voltage higher than the threshold voltage of the selection transistor, Vgnd is ground voltage and Vp0 is second positive voltage; during an erasing operation, a row operation mode is adopted, and the Vwl connected to the gates of the selection transistors in a selected row and a non-selected row is Vpos; the Vwls connected to the gates of the memory transistors in the selected row is Vneg; the Vwls connected to the gates of the memory transistors in the non-selected row is Vpos; the Vbl connected to the drains of the memory transistors in all columns is Vpos; the voltage Vbpw applied to the well region is Vpos; during a programming and writing operation, the row operation mode is adopted; when data “1” is written, the Vwl connected to the gates of the selection transistors in the selected row and the non-selected row is Vneg; the Vwls connected to the gates of the memory transistors in the selected row is Vpos; the Vwls connected to the gates of the memory transistors in the non-selected row is Vneg; the Vbl connected to the drains of the memory transistors in the same column is Vneg, and the voltage Vbpw applied to the well region is Vneg; when data “0” is written, the Vwl connected to the gates of the selection transistors in the selected row and the non-selected row is Vneg; the Vwls connected to the gates of the memory transistors in the selected row is Vpos; the Vwls connected to the gates of the memory transistors in the non-selected row is Vneg; the Vbl connected to the drains of the memory transistors in the same column is Vp0; the voltage Vbpw applied to the well region is Vneg; during a reading operation, the Vwl connected to the gates of the selection transistors in the selected row is Vpwr; the Vwl connected to the gates of the selection transistors in the non-selected row is Vgnd; the Vwls connected to the gates of the memory transistors in the selected row and the non-selected row is Vgnd; the Vbl connected to the drains of the memory transistors in a selected column and a non-selected column is Vgnd; the voltage Vbpw applied to the well region is Vgnd. ### Claim 3 (depends on 2) The memory array according to claim 2, wherein the value of Vp0 is less than Vpos to keep the storage state of the memory transistor unchanged after an operation of writing “0” is completed. ### Claim 4 (depends on 2) The memory array according to claim 2, wherein Vpos is 4V to 12V; Vneg is −8V to −2V; Vpwr is 0V to 3V; Vp0