# US 12,009,029 B2 · System and method applied with computing-in-memory

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- Number: US 12,009,029 B2
- Document ID: US12009029B2
- Status: Granted
- Kind: B2
- Application number: 18/185,312
- Filed: 2023-03-16
- Published: 2023-07-13
- Granted: 2024-06-11
- Earliest claimed: 2021-02-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Der Chih; Meng-Fan Chang; May-Be Chen; Cheng-Xin Xue; Je-Syu Liu
- Web page: https://patentgrep.com/patent/US12009029B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/08: Control thereof
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/0038: {Power supply circuits}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G06F 2207/4814: Non-logic devices, e.g. operational amplifiers
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

## Claims

### Claim 1

A system, comprising:
a multiply-and-accumulate circuit coupled to a memory array and configured to generate a multiply-and-accumulate signal indicating a computational output of the memory array; and
a local generator coupled to the memory array, and configured to generate at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output,
wherein the local generator is further configured to generate an output signal according to the multiply-and-accumulate signal and a summation of the at least one reference signal at the node.

### Claim 2 (depends on 1)

The system of claim 1, further comprising:
a global generator coupled to the memory array to generate the plurality of global signals,
wherein the local generator comprises:
a first reference circuit coupled to the global generator, and configured to generate a first reference signal at the node, in response to a first global signal of the plurality of global signals;
a plurality of second reference circuits coupled to the global generator, and configured to generate a plurality of second reference signals at the node; and
a local current mirror coupled to the first reference circuit at the node, and configured to generate a plurality of local signals, wherein each one of the plurality of local signals is generated by mirroring the summation of the first reference signal and at least one of the plurality of second reference signals at the node.

### Claim 3 (depends on 2)

The system of claim 2, wherein the plurality of second reference circuits are separately activated in response to the plurality of global signals and a plurality of digital signals, and
each one of the plurality of digital signals is associated with a corresponding one in the plurality of second reference signals.

### Claim 4 (depends on 2)

The system of claim 2, wherein a number of the plurality of second reference circuits is associated with the number of the computational output of the memory array.

### Claim 5 (depends on 1)

The system of claim 1, wherein the local generator comprises:
a first reference circuit configured to generate a first reference signal at the node, in response to a first global signal of the plurality of global signals;
a group of second reference circuits configured to generate a plurality of second reference signals, mirrored from the plurality of global signals separately, at the node; and
a group of third reference circuits coupled to the group of the second reference circuits separately, and configured to generate a plurality of third reference signals, mirrored twice from the plurality of global signals separately, at the node.

### Claim 6 (depends on 5)

The system of claim 5, wherein the group of the second reference circuits comprise a second reference circuit that is coupled to a third reference circuit of the group of third reference circuits at the node,
wherein when a value of the first reference signal is less than a value of the multiply-and-accumulate signal,
the second reference circuit is activated to generate a positive-phased reference signal of the plurality of second reference signals at the node, or
the third reference circuit is activated to generate a negative-phased reference signal the plurality of third reference signals at the node, and
one of a plurality of local signals is generated by mirroring the summation of the first reference signal and one of the positive-phased reference signal or the negative-phased reference signal at the node.

### Claim 7 (depends on 1)

The system of claim 1, further comprising:
a global generator coupled to the memory array, and comprising:
a plurality of global circuits configured to generate the plurality of global signals that are different from each other, separately,
wherein the local generator comprises:
a first reference circuit coupled to the global generator, and configured to generate a first reference signal at the node, in response to a first global signal of the plurality of global signals, wherein the first global signal is mirrored from one of the plurality of global circuits to the first reference circuit.

### Claim 8 (depends on 1)

The system of claim 1, wherein the local generator comprises:
a local current mirror coupled to a first reference circuit at the node, and configured to generate a plurality of local signals in different cycles by mirroring a summation of at least one signal at the node; and
a sense amplifier coupled to the local current mirror, and configured to compare each one of the plurality of local signals with the multiply-and-accumulate signal, to generate the output signal for distinguishing candidates of the computational output.

### Claim 9

A system comprising:
at least one local generator coupled to a memory array, comprising:
a current mirror configured to mirror an accumulation of signals at a node to generate a local signal;
a sense amplifier configured to compare the local signals and a multiply-and-accumulate signal output from the memory array to generate a digital signal; and
a plurality of reference circuits coupled to the node, wherein each one of the plurality of reference circuits is configured to generate a corresponding one of a plurality of reference signals transmitted to the node to adjust the accumulation, in response to the digital signal and one of a plurality of global signals that are generated according to a number of a computational output of the memory array.

### Claim 10 (depends on 9)

The system of claim 9, further comprising:
a global generator coupled to the memory array and the at least one local generator, and configured to generate the plurality of global signals,
wherein the plurality of global signals are different from each other and values thereof are proportional to each other.

### Claim 11 (depends on 10)

The system of claim 10, wherein the global generator further comprises:
a plurality of global circuits, wherein each one of the global circuits comprises:
a first transistor of a first conductive type, wherein a first terminal of the first transistor is coupled to a corresponding one of the plurality of reference circuits, and the first terminal and a gate terminal of the first transistor are coupled together; and
a second transistor of a second conductive type, wherein a terminal of the second transistor are coupled to the first terminal of the first transistor, and the second transistor is configured to mirror a corresponding one of the plurality of global signals through the first transistor to the corresponding one of the plurality of reference circuits.

### Claim 12 (depends on 9)

The system of claim 9, wherein the at least one local generator further comprises:
a first reference circuit comprising:
a switch coupled to a global generator, and configured to receive a first global signal of the plurality of global signals output from the global generator; and
a transistor, wherein a gate terminal of the transistor is coupled to the switch, and the transistor is configured to receive the first global signal to generate a first reference signal at a first terminal, coupled to the node, of the transistor.

### Claim 13 (depends on 9)

The system of claim 9, wherein each one of the plurality of reference circuits comprises:
a first switch coupled to a global generator, and configured to receive one of the plurality of global signals output from the global generator when the digital signal has a first logic value; and
a first transistor of a first conductive type, wherein a gate terminal of the first transistor is coupled to the first switch, and the first transistor is configured to receive the one of the plurality of global signals, for mirroring the one of the plurality of global signals to generate a corresponding one of a plurality of reference signals at a first terminal, coupled to the node, of the first transistor.

### Claim 14 (depends on 13)

The system of claim 13, wherein each one of the plurality of reference circuits further comprises:
a second switch coupled to the global generator and the first switch, and configured to receive the one of the plurality of global signals output from the global generator when the digital signal has a second logic value;
a second transistor of the first conductive type, wherein a gate terminal of the second transistor is coupled to the second switch, and the second transistor is configured to receive the one of the plurality of global signals, for generating the corresponding one of a plurality of reference signals mirrored from the global generator; and
a current mirror coupled to a first terminal of the second transistor and the node, and configured to mirror the corresponding one of the plurality of reference signals from the second transistor to the node.

### Claim 15 (depends on 9)

The system of claim 9, wherein the at least one local generator further comprises:
a local current mirror coupled to the plurality of reference circuits at the node,
wherein the local current mirror is configured to mirror the signals accumulated at the node to one of inputs of the sense amplifier.

### Claim 16 (depends on 9)

The system of claim 9, wherein the plurality of reference circuits comprise:
a first group of the reference circuits coupled together at the node, wherein each one of the first group of the reference circuits is configured to receive a corresponding one of the plurality of global signals to generate a corresponding one of the plurality of reference signals with a first phase at the node when the digital signal has a first logic value; and
a second group of the reference circuits coupled together at the node, wherein each one of the second group of the reference circuits is configured to receive the corresponding one of the plurality of global signals to generate the corresponding one of the plurality of reference signals with a second phase at the node when the digital signal has a second logic value.

### Claim 17 (depends on 16)

The system of claim 16, wherein a number of the first group of the reference circuits is equal to a number of the second group of the reference circuits, and is associated with a number of the computational output of the memory array.

### Claim 18

A method, comprising:
turning on, in response to a first output signal of a sense amplifier, one of a first pair of switches to transmit a first global signal to a first reference circuit for generating a reference signal, and outputting a second output signal by comparing the reference signal with a multiply-and-accumulate signal; and
turning on, in response to the second output signal, one of a second pair of switch to transmit a second global signal to a second reference circuit for generating an adjusted reference signal, and outputting a third output signal by comparing the adjusted reference signal with the multiply-and-accumulate signal.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
generating a plurality of global signals comprising the first global signal and the second global signal by a number of global circuits having widths-to-lengths ratios that are different from each other,
wherein the number of the global circuits is associated with a number of a computational output of a memory array.

### Claim 20 (depends on 18)

The method of claim 18, wherein turning on one of the first pair of switches further comprising:
when the first output signal has a first logic value, turning on a first switch of the first pair of switches for mirroring the first global signal to generate the reference signal having a first phase; and
when the first output signal has a second logic value different to the first logic value, turning on a second switch of the first pair of switches for mirroring the first global signal to generate the reference signal having a second phase that is inverse to the first phase.