# US 12,009,027 B2 · Refresh of neighboring memory cells based on read status

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- Number: US 12,009,027 B2
- Document ID: US12009027B2
- Status: Granted
- Kind: B2
- Application number: 17/561,340
- Filed: 2021-12-23
- Published: 2023-06-29
- Granted: 2024-06-11
- Earliest claimed: 2021-12-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Li-Te Chang; Murong Lang; Zhenming Zhou
- Web page: https://patentgrep.com/patent/US12009027B2

## CPC

- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.

## Claims

### Claim 1

A system comprising:
a memory array comprising at least one first memory cell; and
a controller configured to:
read the first memory cell;
determine a read status for the first memory cell;
in response to determining the read status, refresh the first memory cell;
determine errors associated with the first memory cell;
determine, based on the errors, whether at least one criterion is satisfied; and
in response to determining that the criterion is satisfied:
determine a physical address of at least one second memory cell using at least one offset from a physical address of the first memory cell; and
apply a write refresh to the second memory cell.

### Claim 2 (depends on 1)

The system of claim 1, wherein the at least one first memory cell is:
an individual memory cell; or
a plurality of cells associated with a memory unit of the memory array.

### Claim 3 (depends on 1)

The system of claim 1, wherein the second memory cell is on a same wordline as the first memory cell, or is on a same bitline as the first memory cell.

### Claim 4 (depends on 1)

The system of claim 1, wherein the controller is further configured to determine at least one temperature associated with the memory array, and wherein the criterion is adjusted based on the temperature.

### Claim 5 (depends on 1)

The system of claim 1, wherein the at least one offset comprises a bitline offset and a wordline offset.

### Claim 6 (depends on 1)

The system of claim 1, wherein the at least one offset is determined by at least one of adding or subtracting a respective first value to or from a bitline number for each first memory cell, or adding or subtracting a respective second value to a wordline number for each first memory cell.

### Claim 7 (depends on 6)

The system of claim 6, wherein each of the respective first and second values has a value of 1 or 2.

### Claim 8 (depends on 1)

The system of claim 1, wherein:
the at least one criterion includes a first threshold and a second threshold;
the at least one second memory cell is a first set of cells when a number of the errors exceeds the first threshold;
the at least one second memory cell is a second set of cells when the number of the errors exceeds the second threshold;
the second threshold is greater than the first threshold; and
the second set is larger than the first set.

### Claim 9 (depends on 1)

The system of claim 1, wherein the controller is further configured to:
determine a temperature; and
adjust the at least one criterion based on the determined temperature.

### Claim 10 (depends on 9)

The system of claim 9, wherein the temperature is a temperature of a semiconductor die on which the memory array is formed.

### Claim 11 (depends on 9)

The system of claim 9, wherein the criterion is a threshold, and the threshold is a function of temperature.

### Claim 12 (depends on 1)

The system of claim 1, wherein the errors are zero-to-one failures.

### Claim 13 (depends on 1)

The system of claim 1, wherein the memory array is a cross-point memory array.

### Claim 14 (depends on 1)

The system of claim 1, wherein the first memory cell and the second memory cell are each programmable by the controller to be in an amorphous state or a crystalline state.

### Claim 15

An apparatus comprising:
a memory array comprising at least one first memory cell;
at least one sensor; and
a controller configured to:
read the first memory cell;
determine a read status for the first memory cell;
in response to determining the read status, refresh the first memory cell;
determine errors associated with the first memory cell;
collect sensor data from the at least one sensor;
determine, based on the sensor data, at least one criterion;
determine, based on the errors, whether the at least one criterion is satisfied; and
in response to determining that the criterion is satisfied:
determine a physical address of at least one second memory cell based on a physical address of the first memory cell; and
apply a write refresh to the second memory cell.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the sensor is a temperature sensor.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the sensor data is temperature data, the criterion is a threshold, and the threshold is reduced by the controller in response to determining, using the temperature data, that a temperature associated with the memory array has increased.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the physical address of the second memory cell is determined using at least one offset from the physical address of the first memory cell.

### Claim 19 (depends on 15)

The apparatus of claim 15, wherein the read status is a read error due to failure to decode data read from the memory array, and the first memory cell is refreshed in response to determining the read error.

### Claim 20

A method comprising:
reading first memory cells;
determining a read status for the first memory cells;
based on the read status, refreshing the first memory cells;
determining respective physical addresses of second memory cells based on physical addresses of the first memory cells;
determining errors associated with the first memory cells; and
in response to determining that the errors exceed at least one threshold, applying a write refresh to the second memory cells.

### Claim 21 (depends on 20)

The method of claim 20, further comprising adjusting the threshold based on a temperature associated with the memory array.

### Claim 22 (depends on 20)

The method of claim 20, wherein:
the errors are compared to a first threshold and a second threshold;
a first number of second memory cells is refreshed in response to determining that the errors exceed the first threshold; and
a second number of the second memory cells is refreshed in response to determining that the errors exceed the second threshold.