# US 12,009,026 B2 · Precise writing of multi-level weights to memory devices for compute-in-memory

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- Number: US 12,009,026 B2
- Document ID: US12009026B2
- Status: Granted
- Kind: B2
- Application number: 17/117,795
- Filed: 2020-12-10
- Published: 2021-04-01
- Granted: 2024-06-11
- Earliest claimed: 2020-12-10
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Clifford Ong; Yu-Lin Chao; Dmitri E. Nikonov; Ian Young; Eric A. Karl
- Web page: https://patentgrep.com/patent/US12009026B2

## CPC

- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 13/0069: {Writing or programming circuits or methods}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0673: {Single storage device}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0038: {Power supply circuits}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/565: {using capacitive charge storage elements}
- G11C 11/5657: {using ferroelectric storage elements}
- G11C 2013/0052: {Read process characterized by the shape, e.g. form, length, amplitude of the read pulse}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2013/0066: {Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing}
- G11C 2013/009: {Write using potential difference applied between cell electrodes}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

## Claims

### Claim 1

An apparatus comprising:
a non-volatile memory to store a read current that indicates synaptic weight data for an artificial neural network (ANN); and
logic coupled with the memory, wherein the logic is to:
convert the synaptic weight data when input into the logic to generate a base current and an interval current, wherein the base current provides a lower bound current level for the read current, and a combination of the base and interval currents provides an upper bound level for the read current, and wherein the read current indicates the synaptic weight data; and
repeatedly write into the memory, to generate an incremental change in a response current of the memory, until the response current is provided between the lower and upper bound levels for the read current, wherein the response current comprises the read current that indicates the synaptic weight data.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the synaptic weight data correlates to one of a plurality of binary numbers defined by a fixed number of bits, each of the plurality of binary numbers corresponding to a discrete read current level.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the logic comprises a current reference generator to generate the base current and interval current.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the current reference generator comprises a switched transistor ladder configured to generate a plurality of base current levels, each corresponding to one of the plurality of binary numbers, and wherein the interval current is generated from a selected one of the plurality of base current levels and an additional bit to generate additional current levels between each of the plurality of base current levels.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the fixed number of bits plus the additional bit are selected to minimize current distribution overlap between the discrete read current levels.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the non-volatile memory is at least one of a resistive random access memory, ferro-electric field effect transistor (FET) memory, indium gallium zinc oxide FET memory, or phase change memory.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the logic comprises a memory controller to iteratively write and iteratively read in synchronization with a clock.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the memory controller further comprises a pulse generator to create a current pulse to generate the incremental change in the response current of the memory.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the non-volatile memory is adapted to implement compute-in-memory.

### Claim 10

A method, comprising:
generating a base current to provide to a non-volatile memory capable of storing a plurality of discrete current levels, wherein the discrete current levels correspond to synaptic weights to be provided to an artificial neural network (ANN);
generating an interval current above the base current, based at least in part on the generated base current;
calculating a ceiling current that is the sum of the base current and interval current;
reading a current from a memory cell of a non-volatile memory;
writing repeatedly, while the current from the memory cell is less than the ceiling current, a voltage to the memory cell that induces the current read from the memory cell to incrementally increase; and
stopping the writing when the current from the memory cell exceeds the base current,
wherein the base current is generated based upon a selected discrete current level, from the plurality of discrete current levels, that corresponds to a provided synaptic weight.

### Claim 11 (depends on 10)

The method of claim 10, wherein each of the plurality of discrete current levels correspond to one of a plurality of discrete levels expressed by a number of bits, and wherein the interval current is determined at a level expressed by the number of bits plus one or more additional bits.

### Claim 12 (depends on 11)

The method of claim 11, wherein a number of the one or more additional bits are selected to minimize overlap between read current distributions.

### Claim 13 (depends on 10)

The method of claim 10, further comprising generating a clock signal, and wherein the voltage is written to the non-volatile memory in synchronization with the clock signal.

### Claim 14 (depends on 10)

The method of claim 10, wherein generating the base current comprises selecting, from a transistor-based current reference generator, a base current corresponding to a threshold between a selected discrete current level from the plurality of discrete current levels, and a discrete current level that is immediately below the selected discrete current level.

### Claim 15 (depends on 14)

The method of claim 14, wherein the interval current is a predetermined amount equal to:
half a current differential between the selected discrete current level, and
a next discrete current level, from the plurality of discrete current levels, that is above the selected discrete current level.

### Claim 16

A computing device, comprising:
a processor;
a multi-level memory coupled to the processor, the memory adapted to store a level of a plurality of levels of an electrical parameter that indicates a synaptic weight for an artificial neural network; and
memory controller logic coupled to the processor and the memory,
wherein the memory controller logic is configured to:
generate a base reference of the electrical parameter;
generate a ceiling reference of the electrical parameter that is a predetermined interval above the base reference;
read a stored electrical parameter from the multi-level memory;
write repeatedly, while the stored electrical parameter from the memory is less than the ceiling reference, an electrical signal to the memory that causes the stored electrical parameter in the memory to incrementally increase; and
discontinue the write when the stored electrical parameter is greater than the base reference.

### Claim 17 (depends on 16)

The computing device of claim 16, wherein each of the plurality of levels correspond to one of a plurality of discrete levels expressed by a number of bits, and wherein the predetermined interval is determined as a level expressed by the number of bits plus one or more additional bits.

### Claim 18 (depends on 17)

The computing device of claim 17, wherein a number of the one or more additional bits are selected to minimize overlap between distributions of read electrical parameters.

### Claim 19 (depends on 16)

The computing device of claim 16, further comprising an electrical parameter reference generator coupled to the memory controller logic, the reference generator to generate the base reference and the predetermined interval, wherein the predetermined interval corresponds to a threshold between a selected electrical parameter level from the plurality of levels, and a discrete electrical parameter level that is immediately below the selected electrical parameter level.

### Claim 20 (depends on 16)

The computing device of claim 16, wherein the electrical parameter comprises at least one of: current, charge, or voltage.