# US 12,009,025 B2 · Weak precharge before write dual-rail SRAM write optimization

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- Number: US 12,009,025 B2
- Document ID: US12009025B2
- Status: Granted
- Kind: B2
- Application number: 17/358,527
- Filed: 2021-06-25
- Published: 2022-12-29
- Granted: 2024-06-11
- Earliest claimed: 2021-06-25
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Tawfik Ahmed; Andrew J. Robison; Russell J. Schreiber
- Web page: https://patentgrep.com/patent/US12009025B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 7/106: {Data output latches}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/412: using field-effect transistors only
- G11C 11/417: for memory cells of the field-effect type
- G11C 11/418: Address circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.

## Claims

### Claim 1

A method for accessing a memory cell, the method comprising:
enabling precharging of a bit line of the memory cell before a next access of the memory cell;
disabling the precharging after a first interval if the next access is a write; and
disabling the precharging after a second interval if the next access is a read, the first interval being shorter than the second interval,
wherein the bit line is precharged to a memory cell power supply voltage in response to the next access being a read or the next access being a write after a read access, and
wherein the bit line is precharged to a level less than the memory cell power supply voltage prior to a write column select signal cutting off the precharging of the bit line and driving a complementary bit line to ground in response to the next access being a write after a write access.

### Claim 2 (depends on 1)

The method as recited in claim 1,
wherein enabling the precharging comprises setting a bit line precharge control signal of the memory cell to an active level prior to the next access of the memory cell, and
wherein the next access of the memory cell is a write, the precharging is disabled after the first interval, and the disabling comprises resetting the bit line precharge control signal to an inactive level prior to assertion of a word line control signal.

### Claim 3 (depends on 1)

The method as recited in claim 1,
wherein enabling the precharging comprises setting a bit line precharge control signal of the memory cell to an active level prior to the next access of the memory cell, and
wherein the next access of the memory cell is a read, the precharging is disabled after the second interval, and the disabling comprises resetting the bit line precharge control signal to an inactive level concurrently with setting of a word line control signal to a second active level.

### Claim 4 (depends on 1)

The method as recited in claim 1, wherein the first interval is substantially shorter than the second interval.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein a prior access is a read, the next access is a write, and the bit line is precharged to the memory cell power supply voltage.

### Claim 6 (depends on 1)

The method as recited in claim 1,
wherein a prior access is a write, the next access is a write, and the bit line is precharged to at most 90% of the memory cell power supply voltage.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein a memory cell control circuit receives a power supply voltage having a first positive voltage range and the memory cell power supply voltage has a second positive voltage range.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein the write is synchronous to a clock signal having a same frequency as a second clock signal of a processor accessing a memory array including the memory cell.

### Claim 9 (depends on 1)

The method as recited in claim 1, wherein a bit line precharge control signal is asserted concurrently with resetting of a word line control signal to a second inactive level.

### Claim 10

A memory comprising:
a memory cell coupled to a bit line and responsive to a bit line precharge control signal, a write column select signal, and a word line control signal; and
a control circuit configured to generate the bit line precharge control signal, the write column select signal, and the word line control signal to precharge the bit line before a next access of the memory cell, disable the precharging after a first interval if the next access is a write, and disable the precharging after a second interval if the next access is a read, the first interval being shorter than the second interval,
wherein the bit line is precharged to a memory cell power supply voltage in response to the next access being a read or the next access being a write after a read access, and
wherein the bit line is precharged to a level less than the memory cell power supply voltage prior to the write column select signal cutting off the precharging of the bit line and driving a complementary bit line to ground in response to the next access being a write after a write access.

### Claim 11 (depends on 10)

The memory recited in claim 10,
wherein the control circuit asserts the bit line precharge control signal of the memory cell prior to the next access of the memory cell, and
wherein the next access of the memory cell is a write and the control circuit clears the bit line precharge control signal prior to assertion of the word line control signal.

### Claim 12 (depends on 10)

The memory recited in claim 10,
wherein the control circuit asserts the bit line precharge control signal of the memory cell prior to the next access of the memory cell, and
wherein the next access of the memory cell is a read and the control circuit clears the bit line precharge control signal concurrently with assertion of the word line control signal.

### Claim 13 (depends on 10)

The memory recited in claim 10, wherein the first interval is substantially shorter than the second interval.

### Claim 14 (depends on 10)

The memory recited in claim 10, wherein a prior access is a read, the next access is a write, and the bit line is precharged to the memory cell power supply voltage.

### Claim 15 (depends on 10)

The memory recited in claim 10, wherein a prior access is a write, the next access is a write, and the bit line is weakly precharged to at most 90% of the memory cell power supply voltage.

### Claim 16 (depends on 10)

The memory recited in claim 10, wherein the control circuit asserts the word line control signal and concurrently resets the bit line precharge control signal to an inactive level for a read.

### Claim 17 (depends on 10)

The memory recited in claim 10, wherein the control circuit asserts the word line control signal after resetting the bit line precharge control signal to an inactive level for a write.

### Claim 18 (depends on 10)

The memory recited in claim 10, wherein the control circuit receives a power supply voltage having a first positive voltage range and the memory cell power supply voltage has a second positive voltage range.

### Claim 19 (depends on 10)

The memory recited in claim 10, wherein a prior access is a write, the next access is a write, and the bit line is precharged to at most 90% of the memory cell power supply voltage.