# US 12,009,024 B2 · Circuit for reading out data, method for reading out data and memory

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- Number: US 12,009,024 B2
- Document ID: US12009024B2
- Status: Granted
- Kind: B2
- Application number: 17/810,596
- Filed: 2022-07-02
- Published: 2023-09-07
- Granted: 2024-06-11
- Earliest claimed: 2022-03-03
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Xianjun Wu; Weibing Shang
- Web page: https://patentgrep.com/patent/US12009024B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C 11/409: Read-write [R-W] circuits
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.

## Claims

### Claim 1

A circuit for reading out data, applicable for a memory, wherein the memory comprises a read-write control circuit, a column decoding circuit and a plurality of storage areas, and the circuit comprises:
a delay generation circuit, configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and a data transmission delay time of each of the storage areas, and generate a grab enable signal based on all sub-grab signals,
wherein the data transmission delay time of the storage area close to the column decoding circuit is less than the data transmission delay time of the storage area far from the column decoding circuit,
a time interval between a time when the read-write control circuit receives data transmitted from a global data line by each of the storage areas and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range;
the read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal; and
the global data line is configured to read out data of the storage areas through the column decoding circuit based on a column selection signal.

### Claim 2 (depends on 1)

The circuit for reading out data of claim 1, wherein the delay generation circuit comprises:
a delay subcircuit, configured to generate the sub-grab signal corresponding to each of the storage areas;
an integration subcircuit, configured to generate the grab enable signal based on a sub-grab signal corresponding to a storage area to which a word line in an active state belongs.

### Claim 3 (depends on 2)

The circuit for reading out data of claim 2, wherein the delay subcircuit comprises a plurality of delay subunits,
the plurality of delay subunits are connected in series, and
among the plurality of delay subunits connected in series, an input end of a first stage delay subunit is used for receiving the initial grab signal, and a connection line between two adjacent delay subunits and an output end of a last stage delay subunit are used for outputting sub-grab signals corresponding to different storage areas,
wherein different sub-grab signals have different data transmission delay times.

### Claim 4 (depends on 3)

The circuit for reading out data of claim 3, wherein each of the plurality of delay subunits is provided with an even number of inverters, and part of the plurality of delay subunits have different numbers of inverters.

### Claim 5 (depends on 3)

The circuit for reading out data of claim 3, wherein each of the plurality of delay subunits is provided with an even number of inverters, and each of the plurality of delay subunits has a same number of inverters.

### Claim 6 (depends on 2)

The circuit for reading out data of claim 2, wherein the integration subcircuit comprises:
a plurality of primary NAND gates, wherein each of the primary NAND gates corresponds to one of the storage areas, one input end of the primary NAND gate is used for receiving an area indication signal corresponding to the storage area, and another input end of the primary NAND gate is used for receiving the sub-grab signal corresponding to the storage area;
wherein the area indication signal is used for representing the storage area to which the word line in the active state belongs,
output ends of the plurality of primary NAND gates being connected to a same output OR gate, and the output OR gate being used for outputting the grab enable signal.

### Claim 7 (depends on 6)

The circuit for reading out data of claim 6, wherein the delay subcircuit comprises delay transmission wires, the delay transmission wires connect input ends of the plurality of primary NAND gates, the delay subcircuit further comprises a signal end for receiving the initial grab signal, the distance between the signal end and a connection point of the input ends of a primary NAND gate is positively correlated with the data transmission delay time corresponding to the primary NAND gate.

### Claim 8 (depends on 6)

The circuit for reading out data of claim 6, wherein the integration subcircuit further comprises:
a plurality of secondary NAND gates, wherein a number of the secondary NAND gates is less than a number of the primary NAND gates, and each of the secondary NAND gates is connected to at least two of the primary NAND gates;
wherein the output ends of the plurality of primary NAND gates being connected to the same output OR gate, and the output OR gate being used for outputting the grab enable signal comprises: the output ends of the plurality of secondary NAND gates being connected to the same output OR gate.

### Claim 9 (depends on 1)

The circuit for reading out data of claim 1, wherein the delay generation circuit comprises:
a processing subcircuit, configured to acquire, according to an address of an activated word line, a storage area to which the address of the activated word line belongs, and acquire, based on a position of the storage area, a preset value corresponding to the storage area;
a counting subcircuit, connected to the processing subcircuit, configured to receive the initial grab signal, perform counting based on a clock signal, and output the sub-grab signal corresponding to the storage area when a count value is equal to the preset value; and
an integration subcircuit, configured to generate the grab enable signal based on a sub-grab signal corresponding to a storage area to which a word line in an active state belongs.

### Claim 10 (depends on 9)

The circuit for reading out data of claim 9, wherein the delay generation circuit further comprises: a pre-storage subcircuit, wherein the pre-storage subcircuit is connected to the processing subcircuit, and is configured to pre-store a preset value corresponding to each of the storage areas.

### Claim 11 (depends on 9)

The circuit for reading out data of claim 9, wherein the clock signal is an internal clock signal of the memory.

### Claim 12 (depends on 1)

The circuit for reading out data of claim 1, wherein the time interval between the time when the read-write control circuit receives data of each of the storage areas transmitted from the global data line and the time when the read-write control circuit receives the sub-grab signal corresponding to the storage area is equal.

### Claim 13 (depends on 1)

The circuit for reading out data of claim 1, wherein a value of the data transmission delay time is equal to a transmission delay of the data on the global data line between the storage area and the read-write control circuit.

### Claim 14

A method for reading out data, applicable for a data readout circuit, comprising:
reading out data in a memory subcircuit to a global data line based on a column selection signal;
providing an initial grab signal;
generating a sub-grab signal for each of the storage areas based on an initial grab signal and a data transmission delay time of each of the storage areas to cause that a time interval between a time when the read-write control circuit receives data transmitted from a global data line by each of the storage areas and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range,
wherein the data transmission delay time of the storage area close to a column decoding circuit is less than the data transmission delay time of the storage area far from the column decoding circuit,
generating a grab enable signal based on all sub-grab signals; and
reading out data of the global data line to a data bus based on the grab enable signal.

### Claim 15 (depends on 14)

The method for reading out data of claim 14, wherein generating the grab enable signal based on all the sub-grab signals comprises:
generating the grab enable signal by integrating an effective level of each of the sub-grab signals on a same signal; or
generating the grab enable signal by integrating effective levels shared by parts of the sub-grab signals on secondary grab signals and integrating an effective level of each of secondary grab signals on a same signal.

### Claim 16 (depends on 14)

The method for reading out data of claim 14, wherein generating the sub-grab signal for each of the storage areas based on the initial grab signal and data transmission delay time of each of the storage areas comprises:
acquiring a data transmission delay time of the global data line between each of the storage areas and the read-write control circuit; and
generating the sub-grab signal corresponding to each of the storage areas based on the initial grab signal and the data transmission delay time.

### Claim 17 (depends on 14)

The method for reading out data of claim 14, wherein generating the sub-grab signal for each of the storage areas based on the initial grab signal and the data transmission delay time of each of the storage areas:
acquiring an address of an activated word line;
acquiring a storage area to which the activated word line belongs;
acquiring, based on a position of the storage area, a preset value corresponding to the storage area;
performing counting based on the initial grab signal and a clock signal, and
outputting the sub-grab signal of the storage area corresponding to the preset value.

### Claim 18 (depends on 14)

The method for reading out data of claim 14, wherein a value of the data transmission delay time is equal to a transmission delay of the data on the global data line between the storage area and the read-write control circuit.

### Claim 19

A memory, comprising:
a read-write control circuit, a column decoding circuit and a plurality of storage areas;
wherein each of the storage areas is connected to a global data line, and reads out data stored in a memory subcircuit to the global data line based on a column selection signal through the column decoding circuit; and
data on the global data line is read out by using a circuit for reading out data comprising:
a delay generation circuit, configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and the data transmission delay time of each of the storage areas, and generate a grab enable signal based on all sub-grab signals,
wherein the data transmission delay time of the storage area close to a column decoding circuit is less than the data transmission delay time of the storage area far from the column decoding circuit,
a time interval between a time when the read-write control circuit receives data transmitted from a global data line by each of the storage areas and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range;
the read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal; and
the global data line is configured to read out data of the storage areas through the column decoding circuits based on a column selection signal.

### Claim 20 (depends on 19)

The memory of claim 19, wherein the delay generation circuit comprises:
a delay subcircuit, configured to generate the sub-grab signal corresponding to each of the storage areas;
an integration subcircuit, configured to generate the grab enable signal based on a sub-grab signal corresponding to a storage area to which a word line in an active state belongs.