# US 12,009,021 B2 · Device and method for performing matrix operation

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- Number: US 12,009,021 B2
- Document ID: US12009021B2
- Status: Granted
- Kind: B2
- Application number: 17/682,526
- Filed: 2022-02-28
- Published: 2022-09-22
- Granted: 2024-06-11
- Earliest claimed: 2020-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Lien Linus Lu
- Web page: https://patentgrep.com/patent/US12009021B2

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2297: {Power supply circuits}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A system for processing a data array, such as transposing a matrix, includes a two-dimensional array of memory cells, such as FeFETs, each having an input end, an output end and a control end. The system also includes an input interface is adapted to supply signals indicative of a subset of the data array, such as a row of a matrix, and output control signals to the input ends of a selected column of the memory cells. The system further includes an output interface adapted to receive the data stored in the memory array from the output ends of a selected row of the memory cells. A method of processing a data array, such as transposing a matrix, include writing subsets of the data array to the memory array column-by-column, and reading from the memory cells, row-by-row.

## Claims

### Claim 1

A system for implementing a matrix operation, the system comprising:
a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
a plurality of output lines, each connected to the output ends of a respective column of the memory cells;
a plurality of select lines, each connected to the control ends of a respective row of the memory cells; and
an input interface connected to the plurality of input lines and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column or row of values of elements of a matrix, to the input lines;
an output interface connected to the plurality of output lines and adapted to receive from the output lines the elements stored in respective columns of the memory cells; and
a selection signal interface connected to the plurality of select lines and adapted to supply selection signals to the select lines,
wherein the output interface or selection signal interface, or both cooperatively, are adapted to select a column of the plurality of memory cells to enable the column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines,
wherein the input interface or selection signal interface, or both cooperatively, are adapted to select rows of the plurality of memory cells to enable, row-by-row, the plurality of memory cells to output the elements stored in the plurality of memory cells to the output interface.

### Claim 2 (depends on 1)

The system of claim 1, wherein the selection signal interface is adapted to supply a voltage of a first level to all of the selection lines, and the output interface is adapted to supply a voltage of a second level to one of the output lines and a voltage of the first level to the remaining output lines,
wherein the memory elements in the memory array are adapted to be able to store the elements supplied by the input interface through the respective input lines when a voltage of the first level is applied to the control end and a voltage of the second level is applied to the output end, and
wherein the memory elements in the memory array are adapted to be unable to store the elements supplied by the input interface through the respective input lines when a voltage of the first level is applied to both the control end and the output end.

### Claim 3 (depends on 1)

The system of claim 1, wherein each of the memory cells comprises a ferro-electric random-access memory (FeRAM) cell.

### Claim 4 (depends on 1)

The system of claim 1, wherein each of the memory cells comprise a ferro-electric field-effect transistor (FeFET) having a gate, a drain and a source, the gate being connected to the input line associated with the row to which the FeFET belongs, the drain connected to the output line associated with the column to which the FeFET belongs, and the source connected to the select line associated with the row to which the FeFET belongs.

### Claim 5 (depends on 1)

The system of claim 1, wherein the input interface is further adapted to supply output control signals to the input lines, each of the plurality of memory cells being adapted to be enabled or disabled to output the element stored in the memory cell to the respective output line depending on a combination of the output control signal and selection signal applied to the memory cell.

### Claim 6 (depends on 5)

The system of claim 5, wherein the output interface is further adapted to supply input control signals to the output lines, each of the plurality of memory cells being adapted to be enabled or disabled to store the element supplied by the input interface through the respective input line depending on a combination of the input control signal and selection signal applied to the memory cell.

### Claim 7 (depends on 6)

The system of claim 6, wherein the input interface is adapted to supply the elements of a row of a matrix to the respective input lines.

### Claim 8

A system for implementing a matrix operation, the system comprising:
a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
a plurality of output lines, each connected to the output ends of a respective column of the memory cells;
a plurality of select lines, each connected to the control ends of a respective row of the memory cells; and
an input interface connected to the plurality of input lines and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column or row of values of elements of a matrix, to the input lines;
an output interface connected to the plurality of output lines and adapted to receive from the output lines the elements stored in respective columns of the memory cells; and
a selection signal interface connected to the plurality of select lines and adapted to supply selection signals to the select lines,
wherein the output interface or selection signal interface, or both cooperatively, are adapted to select a column of the plurality of memory cells to enable the column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines,
wherein the selection signal interface is adapted to supply a voltage of a first level to all of the selection lines, and the output interface is adapted to supply a voltage of a second level to one of the output lines and a voltage of the first level to the remaining output lines,
wherein the memory elements in the memory array are adapted to be able to store the elements supplied by the input interface through the respective input lines when a voltage of the first level is applied to the control end and a voltage of the second level is applied to the output end, and
wherein the memory elements in the memory array are adapted to be unable to store the elements supplied by the input interface through the respective input lines when a voltage of the first level is applied to both the control end and the output end.

### Claim 9 (depends on 8)

The system of claim 8, wherein the input interface is adapted to supply a voltage of a first level to all of the input lines, and the selection signal interface is adapted to supply a voltage of the first level to one of the selection lines and a voltage of a second level to the remaining selection lines,
wherein the memory elements in the memory array are adapted to be able to output the elements stored in the respective memory elements to the output interface through the respective output lines when a voltage of the first level is applied to both the input end and the control end,
wherein the memory elements in the memory array are adapted to be unable to output the elements stored in the respective memory elements to the output interface through the respective output lines when a voltage of the first level is applied to the input end and a voltage of the second level is applied to the control end.

### Claim 10 (depends on 4)

The system of claim 4, wherein the FeFET has a gate as the input end, a drain as the output end and a source as the control end, and the FeFET has a positive switching voltage and a negative switching voltage and is adapted to be switched on when a gate-source voltage exceeds the positive switch voltage and switched off when the gate-source voltage falls below the positive switch voltage, wherein the input interface is adapted to supply a positive voltage and a negative voltage to each of the input lines, the positive voltage being greater than the positive switching voltage and the negative voltage being lower than the negative switching voltage.

### Claim 11 (depends on 10)

The system of claim 10, wherein the input interface is further adapted to supply a reference voltage different from the positive and negative voltages to each of the input lines.

### Claim 12

A system for processing an input data array having one or more one-dimensional data arrays, each having a set of multi-bit elements, the system comprising:
a plurality of single-bit array processing systems, each comprising:
a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
a plurality of output lines, each connected to the output ends of a respective column of the memory cells; and
a plurality of select lines, each connected to the control ends of a respective row of the memory cells;
an input interface connected to the plurality of input lines of the plurality of single-bit array processing systems and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column or row of values of elements of a matrix, to supply a bit of each of the multi-bit elements of one of the one-dimensional data arrays to each of the respective input lines;
an output interface connected to the plurality of output lines of each single-bit array processing system and adapted to receive from the output lines the elements stored in respective columns of the memory cells; and
a selection signal interface connected to the plurality of select lines of each single-bit processing system and adapted to supply selection signals to the select lines;
wherein the output interface and selection signal interface are adapted to select a column of the plurality of memory cells in each of the plurality of single-bit array processing systems to enable the column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines; and
wherein the input interface and selection signal interface are adapted to select rows of the plurality of memory cells in each of the plurality of single-bit array processing systems to enable, row-by-row, the plurality of memory cells to output the elements stored in of the plurality of memory cells to the output interface.

### Claim 13 (depends on 12)

The system of claim 12, wherein each of the memory cells in each of the single bit processing system comprises a ferro-electric field-effect transistor (FeFET).

### Claim 14 (depends on 12)

The system of claim 12, wherein each bit of each of the multi-bit elements has a place value, wherein the input interface is adapted to supply the bits having the same place value from the plurality of multi-bit elements to the input lines of a respective one of the single-bit processing systems.

### Claim 15 (depends on 14)

The system of claim 14, wherein the output interface is adapted to form an output array of multi-bit elements by grouping the outputs from the single-bit processing systems.

### Claim 16

A method of implementing an array operation, the method comprising:
sequentially applying a plurality of sets of input signals, each set indicative of a respective subset of values of elements of an array, to wordlines of a memory array having a plurality columns and rows of memory cells, each row of the memory cells being associated with a respective one of the wordlines;
storing in the memory array, column-by-column of the memory array, a set of data corresponding to a respective one of the sets of input signals applied to the wordlines; and
reading from the memory array, row-by-row of the memory array, the elements written to the memory cells.

### Claim 17 (depends on 16)

The method of claim 16, wherein each of the memory cells comprises a ferroelectric field-effect transistor (FeFET) having a gate, a source and a drain, wherein the storing in the memory cells of each column comprises applying the respective set of input signals to the gates of the FeFETs in the column via the wordlines, and wherein the reading from each row of the memory array comprises receiving the elements written to the memory cells from the drains of the respect row.

### Claim 18 (depends on 17)

The method of claim 17, wherein the storing in the memory cells of each column further comprises applying a voltage of a first level to all sources of the FeFETs, applying a voltage of a second level to the drains of the FeFETs in the column, and applying a voltage of the first level to the remaining columns of the memory array.

### Claim 19 (depends on 17)

The method of claim 17, wherein the reading of elements from each row further comprises applying a voltage of a first level to all gates of the FeFETs, applying a voltage of the first level to the drains of the FeFETs in the row, and applying a voltage of a second level to the remaining rows of the memory array.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
sequentially applying a plurality of sets of input signals, each set indicative of a respective subset of values of elements of a second array, to wordlines of a second memory array having a plurality columns and rows of memory cells, each row of the memory cells being associated with a respective one of the wordlines;
storing in the memory cells in each column of the second memory array a set of data corresponding to a respective one of the sets of input signals applied to the wordlines;
reading from the second memory array, row-by-row of the second memory array, the elements written to the memory cells; and
forming an array of multi-bit elements, each of the multi-bit elements being a combination of the respective elements read from the two memory arrays.