# US 12,009,020 B2 · Memory device generating optimal write voltage based on size of memory cell and initial write voltage

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- Number: US 12,009,020 B2
- Document ID: US12009020B2
- Status: Granted
- Kind: B2
- Application number: 17/707,027
- Filed: 2022-03-29
- Published: 2022-10-20
- Granted: 2024-06-11
- Earliest claimed: 2021-04-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Daeshik Kim
- Web page: https://patentgrep.com/patent/US12009020B2

## CPC

- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1697: {Power supply circuits}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/20: using counters or linear-feedback shift registers [LFSR]
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/56008: {Error analysis, representation of errors}
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

## Claims

### Claim 1

A memory device comprising:
a memory cell array including a first memory cell region and a second memory cell region;
a voltage generator configured to generate a code corresponding to a write voltage; and
a write driver configured to store data in the first memory cell region in response to the code,
wherein the second memory cell region stores a value defining the write voltage, and
the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein each of the memory cells includes a cell transistor including a first end connected to a source line and a gate electrode connected to a word line, and a magnetic tunneling junction element including a first end connected to a second end of the cell transistor and a second end connected to a bit line.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising:
a first current source configured to generate a first read current;
a second current source configured to generate a second read current; and
a sensing circuit including a sense amplifier configured to amplify a difference between a voltage drop at a first node in response to application of the first read current to a first bit line connected to a selected memory cell among the memory cells and a voltage drop at a second node in response to application of the second read current to a reference bit line.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein a resistance equal to the reference resistance is connected to the reference bit line.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the resistance equal to the reference resistance includes gate poly silicon also forming a gate electrode of a transistor in the memory cell array.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein at least one memory cell having a structure the same as the selected memory cell is connected to the reference bit line.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the write driver includes:
first-type transistors respectively including a first end connected to a first power supply voltage and a second end connected to an output node; and
second-type transistors respectively including a first end connected to a second power supply voltage and a second end connected to the output node.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the code includes a first code and a second code,
the first-type transistors respectively receive at least one bit of the first code, and
the second-type transistors respectively receive at least one bit of the second code.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the second memory cell region is an anti-fuse cell array.

### Claim 10

A method of operating a memory device, the method comprising:
programming memory cells of the memory device to a first state, and iteratively counting fail bits for the memory cells programmed to the first state using a plurality of reference resistances to generate a first counting result;
programming the memory cells of the memory device to a second state, and iteratively counting fail bits for the memory cells programmed to the second state using the plurality of reference resistances to generate a second counting result;
selecting one of the plurality of reference resistances as an optimal reference resistance in response to the first counting result and the second counting result; and
determining a write voltage for the memory device in relation to the optimal reference resistance and an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

### Claim 11 (depends on 10)

The method of claim 10, wherein the selecting of one of the plurality of reference resistances as the optimal reference resistance includes:
summing the first counting result and the second counting result to generate a summing result.

### Claim 12 (depends on 11)

The method of claim 11, wherein the optimal reference resistance corresponds to a fewest number of fail bits in the summing results.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
storing the optimal reference resistance and the write voltage in the memory device.

### Claim 14 (depends on 13)

The method of claim 13, wherein values corresponding to the optimal reference resistance and the write voltage are stored in an anti-fuse array of the memory device.

### Claim 15 (depends on 10)

The method of claim 10, wherein each of the memory cells is a magnetic random access memory (MRAM) cell.

### Claim 16

A memory device comprising:
a memory cell array including a first memory cell region and a second memory cell region;
a column decoder configured to select a bit line connected to a selected memory cell among memory cells in the first memory cell region;
a row decoder configured to drive the bit line connected to the selected memory cell;
a voltage generator configured to generate a code corresponding to a program voltage for the memory device; and
a write driver configured to drive a program current storing data in the selected memory cell in response to the code, and provide the program current to the selected memory cell through the bit line,
wherein the second memory cell region stores a value defining the program voltage and another value defining an optimal reference resistance,
the optimal reference resistance is determined in relation to a first counting result of fail bits for memory cells in the first memory cell region programmed to a first state using a plurality of reference resistances, and a second counting result of fail bits for memory cells in the first memory cell region programmed to a second state using the plurality of reference resistances, and
the program voltage is determined in relation to the optimal reference resistance and an initial program voltage applied to at least one of memory cells of the first memory cell region and memory cells of the second memory cell region.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein each of the memory cells of the first memory cell region includes; a cell transistor including a first end connected to a source line and a gate electrode connected to a word line, and a magnetic tunneling junction element including a first end connected to a second end of the cell transistor and a second end connected to a bit line.

### Claim 18 (depends on 16)

The memory device of claim 16, further comprising:
a sensing circuit including:
a first current source configured to generate a first read current;
a second current source configured to generate a second read current; and
a sense amplifier configured to amplify a difference between a voltage drop at a first node in response to application of the first read current to a bit line connected to the selected memory cell, and a voltage drop at a second node in response to application of the second read current to a reference bit line.

### Claim 19 (depends on 16)

The memory device of claim 16, wherein the write driver includes:
first-type transistors respectively including a first end connected to a first power supply voltage and a second end connected to an output node; and
second-type transistors respectively including a first end connected to a second power supply voltage and a second end connected to the output node.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the code includes a first code and a second code,
the first-type transistors respectively receive at least one bit of the first code, and
the second-type transistors respectively receive at least one bit of the second code.