Display panel and driving method, and display device

A display device, comprising a display panel, wherein the display panel includes:

• a display region and a border region, wherein:
• the display region includes a plurality of pixels and a plurality of data lines extending along a first direction,
• the display region has a first symmetry axis, wherein the first symmetry axis is extended along the first direction,
• the border region includes a data output circuit, and an output end of the data output circuit is electrically connected to a data line of the plurality of data lines,
• the data output circuit includes at least one demultiplexer group and 2L first-demultiplexers disposed on two opposite sides of the first symmetry axis, wherein L is a positive integer, and L1,
• one demultiplexer group of the at least one demultiplexer group is electrically connected to M data lines and includes at least two second-demultiplexers disposed on two opposite sides of the first symmetry axis, and one first-demultiplexer of the 2L first-demultiplexers is electrically connected to N data lines, wherein M=N2, and M and N are positive integers, respectively, and the number of data lines connected to a single second-demultiplexer is at most half of the number of data lines connected to a single first-demultiplexer of the 2L first-demultiplexers,
• each demultiplexer group of the at least one demultiplexer group includes a plurality of second-demultiplexers, and each second-demultiplexer of the plurality of second-demultiplexers is electrically connected to P data lines, wherein N>P1, and P is a positive integer, and
• the plurality of second-demultiplexers share a group of clock signal buses, wherein a portion of the plurality of second-demultiplexers are connected with a portion of the group of clock signal buses, and a remaining portion of the plurality of second-demultiplexers are connected with a remaining portion of the group of clock signal buses.

A driving method of a display panel, wherein:

• the display panel includes:
• a display region and a border region, wherein:
• the display region includes a plurality of pixels and a plurality of data lines extending along a first direction,
• the display region has a first symmetry axis, wherein the first symmetry axis is extended along the first direction,
• the border region includes a data output circuit, and an output end of the data output circuit is electrically connected to a data line of the plurality of data lines,
• the data output circuit includes at least one demultiplexer group and 2L first-demultiplexers disposed on two opposite sides of the first symmetry axis, wherein L is a positive integer, and L1,
• one demultiplexer group of the at least one demultiplexer group is electrically connected to M data lines and includes at least two second-demultiplexers disposed on two opposite sides of the first symmetry axis, and one first-demultiplexer of the 2L first-demultiplexers is electrically connected to N data lines, wherein M=N2, and M and N are positive integers, respectively, and the number of data lines connected to a single second-demultiplexer is at most half of the number of data lines connected to a single first-demultiplexer of the 2L first-demultiplexers,
• each demultiplexer group of the at least one demultiplexer group includes a plurality of second-demultiplexers, and each second-demultiplexer of the plurality of second-demultiplexers is electrically connected to P data lines, wherein N>P1, and P is a positive integer, and
• the plurality of second-demultiplexers share a group of clock signal buses, wherein a portion of the plurality of second-demultiplexers are connected with a portion of the group of clock signal buses, and a remaining portion of the plurality of second-demultiplexers are connected with a remaining portion of the group of clock signal buses;
• and
• the driving method includes:
• receiving image data of a to-be-displayed frame, and
• according to the image data of the to-be-displayed frame, simultaneously outputting, by a driving chip, a signal to each demultiplexer, wherein:
• a signal outputted by the driving chip to each first-demultiplexer of the 2L first-demultiplexers is a grayscale signal obtained according to the image data of the to-be-displayed frame,
• a signal outputted by the driving chip to a second-demultiplexer of the plurality of second-demultiplexers of a demultiplexer group of the at least one demultiplexer group is one of a high-impedance signal and the grayscale signal obtained according to the image data of the to-be-displayed frame, and
• when a signal outputted by the driving chip to the second-demultiplexer of the demultiplexer group is the grayscale signal, a signal outputted by the driving chip to any other second-demultiplexer of the demultiplexer group is the high-impedance signal.