# US 12,008,975 B2 · Display device and operating method thereof

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- Number: US 12,008,975 B2
- Document ID: US12008975B2
- Status: Granted
- Kind: B2
- Application number: 18/142,370
- Filed: 2023-05-02
- Published: 2023-09-21
- Granted: 2024-06-11
- Earliest claimed: 2016-11-25
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Susumu Kawashima; Kouhei Toyotaka; Kei Takahashi
- Web page: https://patentgrep.com/patent/US12008975B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G06F 3/0418: {for error correction or compensation, e.g. based on parallax, calibration or alignment}
- G06F 3/04184: {Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally}
- G06F 3/0443: {using a single layer of sensing electrodes}
- G06F 3/0446: {using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes}
- G02F 1/13338: {Input devices, e.g. touch panels}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G06F 3/044: by capacitive means
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/103: Detection of image changes, e.g. determination of an index representative of the image change
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.

## Claims

### Claim 1

A display device comprising:
a display unit, the display unit comprising:
a touch sensor;
a pixel array;
a source driver electrically connected to a first demultiplexer; and
a plurality of gate drivers sandwiching the pixel array, one of the plurality of gate drivers comprising a first shift register,
wherein the first shift register comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and
a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring,
wherein the first demultiplexer comprises a ninth transistor comprising silicon in a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, the first wiring, and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring, one of a source and a drain of the eighth transistor, one of a source and a drain of the sixth transistor, and one electrode of a second capacitor,
wherein a gate of the fourth transistor is electrically connected to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the fifth transistor, and a gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor.

### Claim 2 (depends on 1)

A smartwatch comprising the display device according to claim 1.

### Claim 3

A display device comprising:
a display unit, the display unit comprising:
a touch sensor;
a pixel array comprising a plurality of pixels, one of the plurality of pixels comprising a light-emitting element;
a source driver electrically connected to a first demultiplexer; and
a plurality of gate drivers sandwiching the pixel array, one of the plurality of gate drivers comprising a first shift register,
wherein the first shift register comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and
a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring,
wherein the plurality of gate drivers and the pixel array are provided over a flexible substrate,
wherein the first demultiplexer comprises a ninth transistor comprising silicon in a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein a first clock signal is supplied to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein a first output signal is output from the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, the first wiring, and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring, one of a source and a drain of the eighth transistor, one of a source and a drain of the sixth transistor, and one electrode of a second capacitor,
wherein a gate of the fourth transistor is electrically connected to the fifth wiring,
wherein a second clock signal is supplied to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the fifth transistor, and a gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor.

### Claim 4 (depends on 3)

A smartwatch comprising the display device according to claim 3.

### Claim 5

A display device comprising:
a display unit, the display unit comprising:
a touch sensor;
a pixel array comprising a plurality of pixels, one of the plurality of pixels comprising a light-emitting element;
a source driver comprising a first shift register, an output terminal of the source driver being electrically connected to a first demultiplexer; and
a plurality of gate drivers sandwiching the pixel array, one of the plurality of gate drivers comprising a second demultiplexer and a second shift register,
wherein the second shift register comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and
a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring,
wherein the plurality of gate drivers and the pixel array are provided over a flexible substrate,
wherein the second demultiplexer comprises a ninth transistor comprising silicon in a channel formation region,
wherein the one of the plurality of pixels comprises a tenth transistor comprising an oxide semiconductor in a channel formation region and an eleventh transistor comprising silicon in a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein a first clock signal is supplied to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein a first output signal is output from the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, the first wiring, and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring, one of a source and a drain of the eighth transistor, one of a source and a drain of the sixth transistor, and one electrode of a second capacitor,
wherein a gate of the fourth transistor is electrically connected to the fifth wiring,
wherein a second clock signal is supplied to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the fifth transistor, and a gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor,
wherein a sixth wiring is electrically connected to one of a source and a drain of the eleventh transistor,
wherein the first wiring is electrically connected to a gate of the eleventh transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to one electrode of a third capacitor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to one electrode of the light-emitting element, and
wherein a first gate of the tenth transistor is electrically connected to a second gate of the tenth transistor.

### Claim 6 (depends on 5)

A smartwatch comprising the display device according to claim 5.