# US 12,008,972 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,972 B2 - Document ID: US12008972B2 - Status: Granted - Kind: B2 - Application number: 18/072,375 - Filed: 2022-11-30 - Published: 2023-06-29 - Granted: 2024-06-11 - Earliest claimed: 2021-12-28 - Assignees: Shanghai Tianma Micro-Electronics Co., Ltd. - Applicants: Shanghai Tianma Micro-Electronics Co., Ltd. - Inventors: Tomohiko Otose - Web page: https://patentgrep.com/patent/US12008972B2 ## CPC - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G11C 19/184: {with field-effect transistors, e.g. MOS-FET} - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2320/02: Improving the quality of display appearance - G09G 2320/043: Preventing or counteracting the effects of ageing - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A display device includes pixel circuit rows, selection lines connected to the pixel circuit rows, and a shift register including linked shift register units. The shift register units output sequential selection pulses to the selection lines. Each of the shift register units outputs the selection pulse to a corresponding selection line among the selection lines. Each of the shift register units includes thin film transistors of a first conductivity type that are connected in parallel, and that, during an ON state, connect the corresponding selection lines to a fixed potential wiring line for applying a non-selection level for the selection pulse. During each frame period, the thin film transistors are turned ON/OFF by clock signals in different phases. The duty cycle of the ON period of each of the thin film transistors during each said frame period is 12.5% or less. ## Claims ### Claim 1 A display device, comprising: a plurality of pixel circuit rows; a plurality of selection lines connected to the plurality of pixel circuit rows; and a shift register including a plurality of linked shift register units, wherein the plurality of shift register units output sequential selection pulses to the plurality of selection lines, wherein each of the plurality of shift register units outputs one of the selection pulses to a corresponding selection line among the plurality of selection lines, wherein each of the shift register units includes a plurality of thin film transistors of a first conductivity type that are connected in parallel, and that, during an ON state, connect the corresponding selection lines to a fixed potential wiring line for applying a non-selection level for the one of the selection pulses, wherein, during each frame period, the plurality of thin film transistors are turned ON/OFF by clock signals in different phases, and wherein the duty cycle of the ON period of each of the plurality of thin film transistors during each said frame period is 12.5% or less. ### Claim 2 (depends on 1) The display device according to claim 1, wherein each of the plurality of thin film transistors is an N-type amorphous silicon thin film transistor, and wherein the non-selection level is a low level. ### Claim 3 (depends on 1) The display device according to claim 1, wherein each shift register unit further includes: a second thin film transistor of the first conductivity type that applies a selection level of the one of the selection pulses to the corresponding selection line in the ON state; and a third thin film transistor of the first conductivity type that connects the fixed potential wiring line to a gate of the second thin film transistor in the ON state, and wherein the third thin film transistor is controlled by a same clock signal as one of the plurality of thin film transistors. ### Claim 4 (depends on 1) The display device according to claim 1, wherein the shift register is a first shift register, wherein the display device further comprises a second shift register that is disposed opposite the first shift register across the plurality of selection lines, wherein the second shift register includes a plurality of linked second shift register units that sequentially output the selection pulses to the plurality of selection lines together with the first shift register, wherein each of the plurality of second shift register units includes a plurality of fourth thin film transistors of the first conductivity type that are connected in parallel, and that, during the ON state, connect the corresponding selection lines to the fixed potential wiring line that applies a non-selection level for the one of the selection pulses, wherein, during each of the frame periods, the plurality of fourth thin film transistors are turned ON/OFF by the clock signals in different phases from each other, the clock signals controlling the fourth thin film transistors being different from the clock signals controlling the thin film transistors of the first shift register, wherein the clock signals of the first shift register have different phases from the clock signals that control the plurality of fourth thin film transistors so that, during each frame period, the thin film transistors of the first shift register and the fourth thin film transistors are turned ON/Off by clock signals in different phases, and wherein the duty cycle of the ON period of each of the plurality of fourth thin film transistors during each said frame period is 12.5% or less. ### Claim 5 (depends on 4) The display device according to claim 4, wherein a difference between a number of the thin film transistors that connect each of the selection lines of the first shift register to the wiring line that applies the non-selection level and a number of the thin film transistors that, in the second shift register, connect each of the selection lines to the fixed potential wiring line that applies the non-selection level is one or less. ### Claim 6 (depends on 5) The display device according to claim 5, wherein a thin film transistor selected from among the plurality of thin film transistors of the first shift register and a fourth thin film transistor selected from among the plurality of fourth thin film transistors are alternately turned ON. ### Claim 7 (depends on 1) The display device according to claim 1, wherein, during each of the frame periods, the plurality of thin film transistors are cyclically and sequentially turned ON/OFF, wherein a floating period during which all of the plurality of thin film transistors are turned OFF is present between consecutive ON periods of the plurality of thin film transistors, and wherein the corresponding selection lines during the floating period are in a floating state. ### Claim 8 (depends on 7) The display device according to claim 7, wherein a length of the consecutive ON periods is less than or equal to a length of the floating period. ### Claim 9 (depends on 1) The display device according to claim 1, wherein, during each of the frame periods, the plurality of thin film transistors are cyclically and sequentially turned ON/OFF, and wherein an end and a start of consecutive ON periods of the plurality of thin film transistors substantially match. ### Claim 10 (depends on 1) The display device according to claim 1, wherein all of the thin film transistors that connect each of the selection lines to the fixed potential wiring line are controlled by the clock signals of different phases.