# US 12,008,962 B2 · Display device and circuit for compensating for mobility characteristic of the display device

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- Number: US 12,008,962 B2
- Document ID: US12008962B2
- Status: Granted
- Kind: B2
- Application number: 17/557,111
- Filed: 2021-12-21
- Published: 2022-06-30
- Granted: 2024-06-11
- Earliest claimed: 2020-12-31
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Lokdam Baek; Hyunho Bae
- Web page: https://patentgrep.com/patent/US12008962B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3225: using an active matrix
- G09G 2300/0413: Details of dummy pixels or dummy lines in flat panels
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
- G09G 2310/0216: Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/061: for resetting or blanking
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0295: by monitoring each display pixel
- G09G 2320/041: Temperature compensation
- G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements
- G09G 2330/045: Protection against panel overheating
- G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof
- G11C 7/1009: {Data masking during input/output}
- G11C 7/1093: {Input synchronization}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A display device includes an N-phase level shifter configured to receive an output cancellation signal, a first reference signal, and a second reference signal from a timing controller, and to output N sensing clock signals to a gate driver, and the gate driver configured to receive the N sensing clock signals from the N-phase level shifter, and to output N sensing output signals to first to n-th gate lines, wherein the N-phase level shifter is configured to receive the output cancellation signal having a number of pulses during a blank period, and the a is at least two.

## Claims

### Claim 1

A display device comprising:
an N-phase level shifter configured to:
receive an output cancellation signal, a first reference signal, and a second reference signal from a timing controller,
count a number of pulses in at least one of the first reference signal and the second reference signal, and
output a plurality of sensing clock signals to a gate driver based on inhibiting output of a number of clock signals corresponding to the number of pulses; and
wherein the gate driver is configured to receive the plurality of sensing clock signals from the N-phase level shifter and to output a plurality of sensing output signals to first to n-th gate lines,
wherein the N-phase level shifter is configured to inhibit output of a portion of the sensing clock signals of the plurality of sensing clock signals based on the number of pulses.

### Claim 2 (depends on 1)

The display device of claim 1, wherein gate lines configured to receive the plurality of sensing output signals are determined based on the output cancellation signal.

### Claim 3 (depends on 2)

The display device of claim 2, wherein the number of gate lines that are sensed during the blank period is equal to the first number.

### Claim 4 (depends on 1)

The display device of claim 1, wherein the output cancellation signal comprises a first pulse defining an interval for a first function of the N-phase level shifter, and a second pulse defining an interval for a second function of the N-phase level shifter.

### Claim 5 (depends on 4)

The display device of claim 4, wherein an order “b” of the sensing clock signal is determined on the basis of the number of pulses that are input during the first pulse, and the number of “b” is ranged between one and N.

### Claim 6 (depends on 5)

The display device of claim 5, wherein, when “b”−1 first reference signals and “b”−1 second reference signals are input during the first pulse, a “b”th sensing clock signal is determined.

### Claim 7 (depends on 6)

The display device of claim 6, wherein the N-phase level shifter is configured to receive one first reference signal and one second reference signal after the first pulse in order to generate the “b”th sensing clock signal.

### Claim 8 (depends on 6)

The display device of claim 6, wherein the N-phase level shifter is configured to output a Q-node charge signal before the “b”th sensing clock signal is output.

### Claim 9 (depends on 5)

The display device of claim 5, wherein an order “c” of the sensing clock signal is determined on the basis of the number of pulses that are input during the second pulse, and the number of “c” is ranged between one and N.

### Claim 10 (depends on 9)

The display device of claim 9, wherein, when “c”−1 first reference signals and “c”−1 second reference signals are input during the second pulse, a “c”th sensing clock signal is determined.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the number of “b” and the number of “c” are different from each other.

### Claim 12 (depends on 10)

The display device of claim 10, wherein the N-phase level shifter is configured to receive one first reference signal and one second reference signal after the second pulse in order to generate the “c”th sensing clock signal.

### Claim 13 (depends on 10)

The display device of claim 10, wherein the N-phase level shifter is configured to output a Q-node discharge signal after the “c”th sensing clock signal is output.

### Claim 14 (depends on 4)

The display device of claim 4, wherein the first function corresponds to identification of gate lines for receiving a next clock signal.

### Claim 15 (depends on 14)

The display device of claim 14, wherein the second function corresponds to timing of pulses of the next clock signal.