# US 12,008,957 B2 · Pixel compensation circuit, display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,957 B2 - Document ID: US12008957B2 - Status: Granted - Kind: B2 - Application number: 17/431,157 - Filed: 2021-06-09 - Published: 2024-01-11 - Granted: 2024-06-11 - Earliest claimed: 2021-05-31 - Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Liuqi Zhang - Web page: https://patentgrep.com/patent/US12008957B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel compensation circuit, a display panel and a display device are disclosed according to an embodiment of the present disclosure. Through detecting the threshold voltage of the driving transistor and offsetting the threshold voltage of the driving transistor from the driving current of the light emitting unit, the driving current becomes unrelated to the threshold voltage of the driving transistor. This could solve the conventional issues of uneven display effect when the driving current of the light emitting unit is affected by the shift of the threshold voltage of the driving transistor. ## Claims ### Claim 1 A pixel compensation circuit, comprising: a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor; wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source; wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node; wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node; wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node; and wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node; wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on; wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off; wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off; wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off; wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off; and wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off. ### Claim 2 (depends on 1) The pixel compensation circuit of claim 1, wherein during the first period, a voltage level of the first node corresponds to a voltage level VDD of the positive electrode of the power source, and a voltage level of the second node corresponds to a voltage level Vi of a reference signal input end; wherein during the second period, the voltage level of the first node corresponds to a threshold voltage Vth of the driving transistor, and the voltage level of the second node corresponds to the voltage level Vi of the reference signal input end; wherein during the third period, the voltage level of the first node corresponds to the threshold voltage Vth of the driving transistor, and the voltage level of the second node corresponds to the voltage level Vi of the reference signal input end; wherein during the fourth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to a voltage level of the data signal input end Vdata; wherein during the fifth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to the voltage level of the data signal input end Vdata; and wherein during the sixth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to the voltage level Vdata of the data signal input end. ### Claim 3 (depends on 2) The pixel compensation circuit of claim 2, wherein the voltage level Vi of the reference signal input end is constant and the voltage level Vi of the reference signal input end is not larger than the voltage level Vdata of the data signal input end. ### Claim 4 (depends on 2) The pixel compensation circuit of claim 2, wherein during the sixth period, a driving current flowing through the driving transistor is I=K(Vdata−Vi)2, where I represents the driving current, K is an intrinsically conductive factor of the driving transistor, Vdata is the voltage level of the data signal input end, and Vi is the voltage level of the reference signal input end. ### Claim 5 (depends on 1) The pixel compensation circuit of claim 1, wherein the driving transistor, the data write-in transistor, the reset transistor and the compensation transistor are P-type thin film transistors (TFT) or N-type TFTs. ### Claim 6 (depends on 1) The pixel compensation circuit of claim 1, wherein the driving transistor, the data write-in transistor, the reset transistor and the compensation transistor are one type of low temperature poly-silicon (LTPS) TFT, oxide semiconductor TFT or amorphous silicon (a-Si) TFT. ### Claim 7 A display panel, comprising: a light emitting unit, having an anode connected to a positive electrode of a power source and a cathode; and a pixel compensation circuit, connected to the cathode of the light emitting unit and, comprising a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor; wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source, a drain of the driving transistor is connected to the cathode of the light emitting unit; wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node; wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node; wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node; and wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node; wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on; wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off; wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off; wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off; wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off; and wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off. ### Claim 8 (depends on 7) The display panel of claim 7, wherein during the first period, a voltage level of the first node corresponds to a voltage level VDD of the positive electrode of the power source, and a voltage level of the second node corresponds to a voltage level Vi of a reference signal input end; wherein during the second period, the voltage level of the first node corresponds to a threshold voltage Vth of the driving transistor, and the voltage level of the second node corresponds to the voltage level Vi of the reference signal input end; wherein during the third period, the voltage level of the first node corresponds to the threshold voltage Vth of the driving transistor, and the voltage level of the second node corresponds to the voltage level Vi of the reference signal input end; wherein during the fourth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to a voltage level of the data signal input end Vdata; wherein during the fifth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to the voltage level of the data signal input end Vdata; and wherein during the sixth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to the voltage level Vdata of the data signal input end. ### Claim 9 (depends on 8) The display panel of claim 8, wherein the voltage level Vi of the reference signal input end is constant and the voltage level Vi of the reference signal input end is not larger than the voltage level Vdata of the data signal input end. ### Claim 10 (depends on 8) The display panel of claim 8, wherein during the sixth period, a driving current flowing through the driving transistor is I=K(Vdata−Vi)2, where I represents the driving current, K is an intrinsically conductive factor of the driving transistor, Vdata is the voltage level of the data signal input end, and Vi is the voltage level of the reference signal input end. ### Claim 11 (depends on 7) The display panel of claim 7, wherein the driving transistor, the data write-in transistor, the reset transistor and the compensation transistor are P-type thin film transistors (TFT) or N-type TFTs. ### Claim 12 (depends on 7) The display panel of claim 7, wherein the driving transistor, the data write-in transistor, the reset transistor and the compensation transistor are one type of low temperature poly-silicon (LTPS) TFT, oxide semiconductor TFT or amorphous silicon (a-Si) TFT. ### Claim 13 A display device, comprising a display panel, the display panel comprising: a light emitting unit, having an anode connected to a positive electrode of a power source and a cathode; and a pixel compensation circuit, connected to the cathode of the light emitting unit and, comprising a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor; wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source, a drain of the driving transistor is connected to the cathode of the light emitting unit; wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node; wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node; wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node; and wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node, wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on; wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off; wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off; wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off; wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off; and wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off. ### Claim 14 (depends on 13) The display device of claim 13, wherein during the first period, a voltage level of the first node corresponds to a voltage level VDD of the positive electrode of the power source, and a voltage level of the second node corresponds to a voltage level Vi of a reference signal input end; wherein during the second period, the voltage level of the first node corresponds to a threshold voltage Vth of the driving transistor, and the voltage level of the second node corresponds to the voltage level Vi of the reference signal input end; wherein during the third period, the voltage level of the first node corresponds to the threshold voltage Vth of the driving transistor, and the voltage level of the second node corresponds to the voltage level Vi of the reference signal input end; wherein during the fourth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to a voltage level of the data signal input end Vdata; wherein during the fifth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to the voltage level of the data signal input end Vdata; and wherein during the sixth period, the voltage level of the first node corresponds to Vdata−Vi+Vth, and the voltage level of the second node corresponds to the voltage level Vdata of the data signal input end. ### Claim 15 (depends on 14) The display device of claim 14, wherein the voltage level Vi of the reference signal input end is constant and the voltage level Vi of the reference signal input end is not larger than the voltage level Vdata of the data signal input end. ### Claim 16 (depends on 14) The display device of claim 14, wherein during the sixth period, a driving current flowing through the driving transistor is I=K(Vdata−Vi)2, where I represents the driving current, K is an intrinsically conductive factor of the driving transistor, Vdata is the voltage level of the data signal input end, and Vi is the voltage level of the reference signal input end. ### Claim 17 (depends on 13) The display device of claim 13, wherein the driving transistor, the data write-in transistor, the reset transistor and the compensation transistor are P-type thin film transistors (TFT) or N-type TFTs. ### Claim 18 (depends on 13) The display device of claim 13, wherein the driving transistor, the data write-in transistor, the reset transistor and the compensation transistor are one type of low temperature poly-silicon (LTPS) TFT, oxide semiconductor TFT or amorphous silicon (a-Si) TFT.