# US 12,008,952 B2 · Pixel, display device including pixel, and pixel driving method

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- Number: US 12,008,952 B2
- Document ID: US12008952B2
- Status: Granted
- Kind: B2
- Application number: 18/224,452
- Filed: 2023-07-20
- Published: 2024-04-04
- Granted: 2024-06-11
- Earliest claimed: 2022-09-30
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., LTD.
- Inventors: Jin-Wook Yang; Yu-Chol Kim; Donggyu Lee; Jae-Hyeon Jeon
- Web page: https://patentgrep.com/patent/US12008952B2

## CPC

- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0216: Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD
- G09G 2340/0435: Change or adaptation of the frame rate of the video stream
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A pixel includes: a light-emitting element including an anode and a cathode, a first transistor including a first and a second electrode and a gate electrode connected with a first node, a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected with a first scan line, a sixth transistor connected between the second electrode of the first transistor and the anode and including a gate electrode connected with a first emission line, and a seventh transistor connected between the anode and an initialization voltage line and including a gate electrode connected with a second scan line. During an initialization period, the third, sixth, and seventh transistors are turned on such that an initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor.

## Claims

### Claim 1

A pixel comprising:
a light-emitting element including an anode and a cathode;
a first transistor including a first electrode, a second electrode, and a gate electrode connected with a first node;
a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected with a first scan line;
a sixth transistor connected between the second electrode of the first transistor and the anode of the light-emitting element and including a gate electrode connected with a first emission line; and
a seventh transistor connected between the anode of the light-emitting element and an initialization voltage line and including a gate electrode connected with a second scan line,
wherein, during an initialization period, the third, sixth, and seventh transistors are turned on such that an initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor.

### Claim 2 (depends on 1)

The pixel of claim 1, wherein, during the initialization period, a first scan signal provided to the first scan line, a second scan signal provided to the second scan line, and a first emission signal provided to the first emission line are at an active level.

### Claim 3 (depends on 1)

The pixel of claim 1, further comprising:
an eighth transistor connected between a driving voltage line and the first electrode of the first transistor and including a gate electrode connected with a second emission line;
a fifth transistor connected between the first electrode of the first transistor and a second node and including a gate electrode connected with the first scan line; and
a capacitor connected between the first node and the second node.

### Claim 4 (depends on 3)

The pixel of claim 3, wherein, during a compensation period, the eighth transistor and the fifth transistor are turned on such that a driving voltage is transferred from the driving voltage line to the second node.

### Claim 5 (depends on 4)

The pixel of claim 4, wherein, during the compensation period, the third transistor and the eighth transistor are turned on such that the driving voltage is transferred to the first node through the eighth transistor, the first transistor, and the third transistor.

### Claim 6 (depends on 4)

The pixel of claim 4, wherein, during the compensation period, a first scan signal provided to the first scan line and a second emission signal provided to the second emission line are at an active level.

### Claim 7 (depends on 4)

The pixel of claim 4, wherein the initialization period and the compensation period are repeated in turn plural times.

### Claim 8 (depends on 3)

The pixel of claim 3, further comprising:
a second transistor connected between a data line and the second node and including a gate electrode connected with a third scan line.

### Claim 9 (depends on 1)

The pixel of claim 1, further comprising:
a fourth transistor connected between the first electrode of the first transistor and a bias voltage line and including a gate electrode connected with a fourth scan line.

### Claim 10 (depends on 1)

The pixel of claim 1, further comprising:
an eighth transistor connected between a driving voltage line and the first electrode of the first transistor and including a gate electrode connected with a second emission line;
a fifteenth transistor connected between the driving voltage line and a second node and including a gate electrode connected with the first scan line; and
a capacitor connected between the first node and the second node.

### Claim 11 (depends on 10)

The pixel of claim 10, wherein, during a compensation period, the fifteenth transistor is turned on such that a driving voltage from the driving voltage line is transferred to the second node.

### Claim 12 (depends on 1)

The pixel of claim 1, further comprising:
an eighth transistor connected between a driving voltage line and the first electrode of the first transistor and including a gate electrode connected with a second emission line; and
a capacitor connected between the first node and a second node.

### Claim 13 (depends on 12)

The pixel of claim 12, further comprising:
a fifth transistor connected between the first electrode of the first transistor and the second node and including a gate electrode connected with a fifth scan line,
wherein the first transistor is an P-type transistor, and the fifth transistor is an N-type transistor.

### Claim 14 (depends on 13)

The pixel of claim 13, further comprising:
a second transistor connected between a data line and the first electrode of the first transistor and including a gate electrode connected with a third scan line; and
a ninth transistor connected between a bias voltage line and the first electrode of the first transistor and including a gate electrode connected with a fourth scan line.

### Claim 15 (depends on 12)

The pixel of claim 12, further comprising:
a fifth transistor connected between the first electrode of the first transistor and the second node and including a gate electrode connected with the first scan line.

### Claim 16 (depends on 12)

The pixel of claim 12, further comprising:
a second transistor connected between a data line and a third node and including a gate electrode connected with a third scan line; and
a tenth transistor connected between the second node and the third node and including a gate electrode connected with a fifth scan line,
wherein the second transistor is a P-type transistor, and the tenth transistor is an N-type transistor.

### Claim 17 (depends on 12)

The pixel of claim 12, further comprising:
an eleventh transistor connected between the first node and a fourth node and including a gate electrode connected with a fifth scan line; and
a fourth transistor connected between the fourth node and an initialization voltage line and including a gate electrode connected with a sixth scan line,
wherein the eleventh transistor is an N-type transistor, and the fourth transistor is a P-type transistor.

### Claim 18 (depends on 12)

The pixel of claim 12, further comprising:
a fourth transistor connected between the first node and an initialization voltage line and including a gate electrode connected with a sixth scan line,
wherein the third transistor is an N-type transistor, and the fourth transistor is an N-type transistor.

### Claim 19 (depends on 16)

The pixel of claim 16, further comprising:
a twenty-fifth transistor connected between the third node and a reference voltage line and including a gate electrode connected with the first scan line,
wherein each of the first transistor and the sixth transistor is a P-type transistor, and each of the third transistor and the twenty-fifth transistor is an N-type transistor.

### Claim 20 (depends on 1)

The pixel of claim 1, further comprising:
a capacitor connected between the first node and a second node;
a second transistor connected between a data line and a third node and including a gate electrode connected with a third scan line;
a tenth transistor connected between the second node and the third node and including a gate electrode connected with a fifth scan line; and
a twenty-fifth transistor connected between the third node and a reference voltage line and including a gate electrode connected with the first scan line,
wherein each of the first transistor and the second transistor is a P-type transistor, and each of the tenth transistor and the twenty-fifth transistor is an N-type transistor.

### Claim 21 (depends on 1)

The pixel of claim 1, further comprising:
a second transistor connected between a data line and the first electrode of the first transistor and including a gate electrode connected with a third scan line.

### Claim 22 (depends on 3)

The pixel of claim 3, further comprising:
a second transistor connected between a data line and a third node and including a gate electrode connected with a third scan line;
a tenth transistor connected between the second node and the third node and including a gate electrode connected with a fifth scan line;
a fifth transistor connected between the first electrode of the first transistor and the third node and including a gate electrode connected with the first scan line;
an eleventh transistor connected between the first node and a fourth node and including a gate electrode connected with the fifth scan line; and
a fourth transistor connected between the fourth node and an initialization voltage line and including a gate electrode connected with a sixth scan line,
wherein each of the second transistor and the fourth transistor is P-type transistor, and each of the tenth transistor and the eleventh transistor is an N-type transistor.

### Claim 23

A display device comprising:
a display panel including a pixel connected with a plurality of scan lines, a plurality of emission lines, and a data line;
a scan driving circuit configured to drive the plurality of scan lines in response to a scan control signal;
a driving controller configured to output the scan control signal; and
a voltage generator configured to generate a driving voltage and an initialization voltage,
wherein the pixel includes:
a light-emitting element including an anode and a cathode;
a first transistor including a first electrode, a second electrode, and a gate electrode connected with a first node;
a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected with a first scan line;
a sixth transistor connected between the second electrode of the first transistor and the anode of the light-emitting element and including a gate electrode connected with a first emission line; and
a seventh transistor connected between the anode of the light-emitting element and an initialization voltage line and including a gate electrode connected with a second scan line,
wherein, during an initialization period, the third, sixth, and seventh transistors are turned on such that the initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor.

### Claim 24 (depends on 23)

The display device of claim 23, further comprising:
a fifth transistor connected between the first electrode of the first transistor and a second node and including a gate electrode connected with the first scan line; and
a capacitor connected between the first node and the second node.

### Claim 25 (depends on 24)

The display device of claim 24, wherein the first transistor is a P-type transistor, and each of the third transistor and the fifth transistor is an N-type transistor.

### Claim 26

A method of driving a pixel which includes a first transistor including a first electrode, a second electrode, and a gate electrode and a capacitor connected between a first node and a second node, the method comprising:
an initialization step in which a third transistor, a seventh transistor, and a sixth transistor are turned on by a first scan signal, a second scan signal, and a first emission signal being at an active level, respectively, such that an initialization voltage is transferred to the gate electrode of the first transistor; and
a compensation step in which a fifth transistor is turned on by a certain scan signal of the active level such that a driving voltage is transferred to the second node.

### Claim 27 (depends on 26)

The method of claim 26, wherein the third transistor, the sixth transistor, and the seventh transistor are connected sequentially in series between the gate electrode of the first transistor and an initialization voltage line through which the initialization voltage is transferred, and
wherein the initialization step includes:
providing the first scan signal of the active level to a gate electrode of the third transistor;
providing the first emission signal of the active level to a gate electrode of the sixth transistor; and
providing the second scan signal of the active level to a gate electrode of the seventh transistor.

### Claim 28 (depends on 26)

The method of claim 26, wherein the certain scan signal includes the first scan signal, and
wherein the compensation step includes:
providing the first scan signal of the active level to a gate electrode of the fifth transistor.

### Claim 29 (depends on 26)

The method of claim 26, wherein the certain scan signal includes a fifth scan signal, and
wherein the compensation step includes:
providing the fifth scan signal of the active level to a gate electrode of the fifth transistor.