# US 12,008,945 B1 · Tiling display apparatus and output synchronization method thereof

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- Number: US 12,008,945 B1
- Document ID: US12008945B1
- Status: Granted
- Kind: B1
- Application number: 18/226,546
- Filed: 2023-07-26
- Published: 2024-07-04
- Granted: 2024-06-11
- Earliest claimed: 2022-12-30
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Sang Woo Park; Tae Gung Kim
- Web page: https://patentgrep.com/patent/US12008945B1

## CPC

- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 2300/026: Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
- G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0242: Compensation of deficiencies in the appearance of colours
- G09G 2320/0626: for control of overall brightness
- G09G 2320/0673: for control of gamma adjustment, e.g. selecting another gamma curve
- G09G 2360/16: Calculation or use of calculated indices related to luminance levels in display data
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A tiling display apparatus comprises: a first display group including first timing controllers to receive a first input data enable signal from a first system chip, the first input data enable signal having a first delay; and a second display group including second timing controllers to receive a second input data enable signal from a second system chip, the second input data enable signal having a second delay, wherein the first timing controllers of the first display group and the second timing controllers of the second display group share input delay information about the first delay of the first input data enable signal and input delay information about the second delay of the second input data enable signal with each other, and each of the first timing controllers and the second timing controllers generate a common output data enable signal based on the shared input delay information.

## Claims

### Claim 1

A tiling display apparatus comprising:
a first display group including first timing controllers configured to receive a first input data enable signal that is synchronized with a first input image from a first system chip, the first input data enable signal having a first delay; and
a second display group including second timing controllers configured to receive a second input data enable signal that is synchronized with a second input image from a second system chip, the second input data enable signal having a second delay that is different from the first delay,
wherein the first timing controllers of the first display group and the second timing controllers of the second display group share input delay information about the first delay of the first input data enable signal and input delay information about the second delay of the second input data enable signal with each other, and each of the first timing controllers and the second timing controllers generate a common output data enable signal based on the input delay information about the first delay and the input delay information about the second delay, and
wherein an output timing of the first input image to display the first input image matches an output timing of the second input image to display the second input image based on the common output data enable signal generated by each of the first timing controllers and the second timing controllers.

### Claim 2 (depends on 1)

The tiling display apparatus of claim 1, wherein the first timing controllers of the first display group and the second timing controllers of the second display group determine which of the first input data enable signal and the second input data enable signal has a longest amount of delay based on the input delay information about the first delay of the first input data enable signal and the input delay information about the second delay of the second input data enable signal, and each of the first timing controllers and the second timing controllers generates the common output data enable signal with respect to the determined input data enable signal having the longest amount of delay.

### Claim 3 (depends on 1)

The tiling display apparatus of claim 1, wherein the first timing controllers of the first display group synchronize common output data enable signals generated by the first timing controllers with a timing at which the first input image is output to a tiling screen included in the first display group, and the second timing controllers of the second display group synchronize common output data enable signals generated by the second timing controllers with a timing at which the second input image is output to a tiling screen included in the second display group.

### Claim 4 (depends on 1)

The tiling display apparatus of claim 1, further comprising:
a first type of interface circuit configured to connect together the first timing controllers of the first display group and connect together the second timing controllers of the second display group,
wherein the first timing controllers of the first display group are configured to sequentially receive the first input data enable signal that is synchronized with the first input image via the first type of interface circuit and the second timing controllers of the second display group are configured to sequentially receive the second input data enable signal synchronized with the second input image via the first type of interface circuit, and
wherein one of the first timing controllers of the first display group is connected with the first system chip via the first type of interface circuit, and one of the second timing controllers of the second display group is connected with the second system chip via the first type of interface circuit.

### Claim 5 (depends on 4)

The tiling display apparatus of claim 4, further comprising:
a second type of interface circuit that is different from the first type of interface circuit,
wherein the first timing controllers of the first display group and the second timing controllers of the second display group are connected with each other via the second type of interface circuit and share the input delay information about the first delay and the input delay information about the second delay with each other via the second type of interface circuit, and
wherein one of the first timing controllers of the first group is connected with one of the second timing controllers of the second group via the second type of interface circuit.

### Claim 6 (depends on 5)

The tiling display apparatus of claim 5, wherein each of the first display group and the second display group comprises a plurality of displays, and the first timing controllers of the first display group share first average picture level information of the first input image for display by the plurality of display included in the first display group with the second timing controllers of the second display group via the second type of interface circuit, and the second timing controllers of the second display group share second average picture level information about the second input image for display by the plurality of displays included in the second display group with the first timing controllers of the first display group via the second type of interface circuit.

### Claim 7 (depends on 6)

The tiling display apparatus of claim 6, wherein the first timing controllers of the first display group and the second timing controllers of the second group share the input delay information about the first delay and the input delay information about the second delay based on the first average picture level information and the second average picture level information.

### Claim 8 (depends on 7)

The tiling display apparatus of claim 7, wherein the first average picture level information comprises first timing information indicative of when to start sharing the first average picture level information based on the first delay of the first input data enable signal, and the second average picture level information comprises second timing information indicative of when to start sharing the second average picture level information based on the second delay of the second input data enable signal.

### Claim 9

A tiling display device comprising:
a plurality of system chips configured to output a plurality of input data enable signals having different delays, each of the plurality of input data enable signals synchronized with a corresponding portion of an input image; and
a plurality of display groups that are each configured to receive a corresponding input data enable signal from the plurality of input data enable signals and display a corresponding portion of the input image, each of the plurality of display groups including a plurality of timing controllers that are each configured to:
receive delay information indicative of different delays of the plurality of input data enable signals from one or more other timing controllers from the plurality of timing controllers;
determine a longest delay of the different delays from the received delay information; and
generate a corresponding output data enable signal based on the longest delay, the corresponding output data enable signal indicative of when the display group displays the corresponding portion of the input image,
wherein output data enable signals generated by the plurality of timing controllers have a same timing at which each of the plurality of display groups displays the corresponding portion of the image.

### Claim 10 (depends on 9)

The tiling display device of claim 9, wherein each of the plurality of timing controllers is further configured to:
receive, from one system chip from the plurality of system chips, a corresponding input data enable signal from the plurality of input data enable signals that is synchronized with the portion of the input image, the corresponding input data enable signal having a delay.

### Claim 11 (depends on 10)

The tiling display device of claim 10, further comprising:
a first type of interface circuit configured to connect together the plurality of timing controllers included each of the plurality of display groups, and one of the plurality of timing controllers included in each of the plurality of display groups is connected with a corresponding one of the plurality of system chips via the first type of interface circuit, wherein the plurality of timing controllers included in each of the plurality of display groups are configured to sequentially propagate the corresponding input data enable signal received from the one of the plurality of system chips amongst the plurality of timing controllers in the display group via the first interface circuit; and
a second type of interface circuit that is different from the first type of interface circuit, wherein the plurality of timing controllers across all of the plurality of display groups are connected with each other via the second type of interface circuit and share the delay information indicative of different delays of the plurality of input data enable signals with each other via the second type of interface circuit.

### Claim 12 (depends on 11)

The tiling display device of claim 11, wherein the plurality of display groups are arranged into a plurality of rows of display groups, and a timing controller included in a first display group positioned in a first row of the plurality of rows of display groups receives delay information indicative of a delay of an input data enable signal received by a second display group positioned in a last row of the plurality of rows of display groups from a timing controller included in a third display group that is located in the first row via the second type of interface circuit.

### Claim 13 (depends on 11)

The tiling display device of claim 11, wherein the first type of interface circuit is configured for unidirectional communication and the second type of interface circuit is configured for bidirectional communication.

### Claim 14 (depends on 9)

The tiling display device of claim 9, wherein the plurality of timing controllers included in each of the plurality of display groups are further configured to:
calculate average picture level information of the corresponding portion of the input image configured to be displayed by the display group; and
receive average picture level information of other portions of the input image from the one or more other timing controllers included in at least one other display group from the plurality of display groups.

### Claim 15

A tiling display device comprising:
a plurality of system chips configured to output a plurality of input data enable signals having different delays, each of the plurality of input data enable signals synchronized with a corresponding portion of an input image;
a plurality of display groups arranged in a plurality of rows of display groups, each display group including a plurality of timing controllers;
a plurality of first interfaces configured to receive the plurality of input data enable signals, each first interface configured to connect together the plurality of timing controllers included in a corresponding display group from the plurality of display groups and connect one timing controller from the plurality of timing controllers included in the corresponding display group to a corresponding one of the plurality of system chips; and
a second interface configured to connect together the plurality of timing controllers across all of the plurality of display groups.

### Claim 16 (depends on 15)

The tiling display device of claim 15, wherein the plurality of first interfaces are configured for unidirectional communication and the second interface is configured for bidirectional communication.

### Claim 17 (depends on 16)

The tiling display device of claim 16, wherein each of the plurality of display groups is configured to receive a corresponding input data enable signal from the plurality of input data enable signals from the corresponding one of the plurality of system chips via the first interface that is connected to the one timing controller included in the display group.

### Claim 18 (depends on 17)

The tiling display device of claim 17, wherein each of the plurality of timing controllers across all of the plurality of display groups is configured to share delay information associated with the corresponding input data enable signal received by the display group that includes the timing controller with all remaining timing controllers across the plurality of display groups via the second interface.

### Claim 19 (depends on 18)

The tiling display device of claim 18, wherein each of the plurality of timing controllers across all of the plurality of display groups is configured to determine a longest delay amongst the plurality of input data enable signals based on the shared delay information and generate a corresponding output data enable signal based on the longest delay that is indicative of when the display group that includes the timing controller displays the corresponding portion of the input image,
wherein output data enable signals generated by the plurality of timing controllers have a same timing at which each of the plurality of display groups displays the corresponding portion of the image.