# US 12,008,940 B1 · Gate drive circuits and display panels

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,008,940 B1
- Document ID: US12008940B1
- Status: Granted
- Kind: B1
- Application number: 18/357,252
- Filed: 2023-07-24
- Granted: 2024-06-11
- Earliest claimed: 2023-03-01
- Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Bin Yuan; Fang Qin; Cheng Chen
- Web page: https://patentgrep.com/patent/US12008940B1

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3266: Details of drivers for scan electrodes
- H03K 17/6872: {using complementary field-effect transistors}
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A gate drive circuit includes a plurality of gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage, and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses. At least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage includes three transistors with the same channel type.

## Claims

### Claim 1

A display panel comprising:
a pixel circuit comprising a writing transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and
a gate drive circuit comprising a plurality of cascaded gate drive units, wherein each of the gate drive units comprises:
a stage transmission signal selection circuit electrically connected between a first wiring and a first node;
a pull-up control circuit configured to control a potential of a second node based on a potential of the first node and a potential of a first clock signal;
a pulse number reduction circuit electrically connected between the second node and a third node, the pulse number reduction circuit having a control terminal electrically connected to a reset line;
a first inversion circuit connected between the second node and a fourth node;
a first output stage configured to output a first gate control signal based on a potential of the third node and a potential of the fourth node; and
a second output stage configured to output a second gate control signal based on the potential of the second node,
wherein a number of pulses of the second gate control signal in one frame is greater than a number of pulses of the first gate control signal in one frame,
at least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage comprises three transistors with a same channel type, and
the first output stage has an output terminal electrically connected to a gate of the writing transistor, and the second output stage has an output terminal electrically connected to a gate of the compensation transistor.

### Claim 2 (depends on 1)

The display panel of claim 1, wherein the first gate control signal is an N-th stage negative pulse scanning signal, the second gate control signal is an N-th stage positive pulse scanning signal, and the control terminal of the pulse number reduction circuit is configured to an (N-X)-th stage positive pulse scanning signal, where N is an integer greater than or equal to 1 and X is an integer greater than or equal to 2.

### Claim 3 (depends on 2)

The display panel of claim 2, wherein the pixel circuit further comprises a first initialization transistor configured to initialize a potential of the gate of the drive transistor, the first initialization transistor having a gate for receiving the (N-X)-th stage positive pulse scanning signal.

### Claim 4 (depends on 2)

The display panel of claim 2, wherein the stage transmission signal selection circuit is configured to receive one of a start control signal and an (N-Y)-th stage positive pulse scanning signal, where Y is an integer greater than or equal to 1.

### Claim 5 (depends on 1)

The display panel of claim 1, wherein the at least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage comprises:
a first transistor, wherein one of a source of the first transistor and a drain of the first transistor is electrically connected to a low potential line, a gate of the first transistor is electrically connected to the first wiring, and the first transistor is a P-channel type thin film transistor;
a second transistor, wherein a gate of the second transistor is electrically connected to the gate of the first transistor, one of a source of the second transistor and a drain of the second transistor is electrically connected to a high potential line, another one of the source of the second transistor and the drain of the second transistor is electrically connected to the first node, and the second transistor is a P-channel type thin film transistor; and
a third transistor, wherein a gate of the third transistor is electrically connected to another one of the source of the first transistor and the drain of the first transistor, one of a source of the third transistor and a drain of the third transistor is electrically connected to the low potential line, another one of the source of the third transistor and the drain of the third transistor is electrically connected to the first node, and the third transistor is a P-channel type thin film transistor.

### Claim 6 (depends on 5)

The display panel of claim 5, wherein a ratio of a width of a channel of the first transistor to a length of the channel of the first transistor is greater than 1.5, a ratio of a width of a channel of the second transistor to a length of the channel of the second transistor is in a range of 0.5-3, and a ratio of a width of a channel of the third transistor to a length of the channel of the third transistor is in a range of 0.5-3.

### Claim 7 (depends on 1)

The display panel of claim 1, wherein the pulse number reduction circuit comprises a fourth transistor, one of a source of the fourth transistor and a drain of the fourth transistor is electrically connected to the second node, another one of the source of the fourth transistor and the drain of the fourth transistor is electrically connected to the third node, and a gate of the fourth transistor is electrically connected to the reset line.

### Claim 8 (depends on 7)

The display panel of claim 7, wherein a ratio of a width of a channel of the fourth transistor to a length of the channel of the fourth transistor is greater than or equal to 0.5 and less than or equal to 1.5.

### Claim 9 (depends on 7)

The display panel of claim 7, wherein the pulse number reduction circuit further comprises a first capacitor, a terminal of the first capacitor is electrically connected to the gate of the fourth transistor, and another terminal of the first capacitor is electrically connected to the another one of the source of the fourth transistor and the drain of the fourth transistor.

### Claim 10 (depends on 9)

The display panel of claim 9, wherein the first output stage comprises:
a pull-up transistor, wherein a gate of the pull-up transistor is electrically connected to the third node, one of a source of the pull-up transistor and a drain of the pull-up transistor is electrically connected to a second clock line, and another one of the source of the pull-up transistor and the drain of the pull-up transistor is configured to output the first gate control signal; and
a second capacitor, wherein a terminal of the second capacitor is electrically connected to the gate of the pull-up transistor and another terminal of the second capacitor is electrically connected to the another one of the source of the pull-up transistor and the drain of the pull-up transistor,
wherein a ratio of a capacity of the first capacitor to a capacity of the second capacitor is greater than or equal to 0.5.

### Claim 11

A gate drive circuit comprising a plurality of cascaded gate drive units, wherein each of the gate drive units comprises:
a stage transmission signal selection circuit electrically connected between a first wiring and a first node;
a pull-up control circuit configured to control a potential of a second node based on a potential of the first node and a potential of a first clock signal;
a pulse number reduction circuit electrically connected between the second node and a third node, the pulse number reduction circuit having a control terminal electrically connected to a reset line;
a first inversion circuit connected between the second node and a fourth node;
a first output stage configured to output a first gate control signal based on a potential of the third node and a potential of the fourth node; and
a second output stage configured to output a second gate control signal based on the potential of the second node,
wherein a number of pulses of the second gate control signal in one frame is greater than a number of pulses of the first gate control signal in one frame; and
at least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage comprises three transistors with a same channel type.

### Claim 12 (depends on 11)

The gate drive circuit of claim 11, wherein the at least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage comprises:
a first transistor, wherein one of a source of the first transistor and a drain of the first transistor is electrically connected to a low potential line, a gate of the first transistor is electrically connected to the first wiring, and the first transistor is a P-channel type thin film transistor;
a second transistor, wherein a gate of the second transistor is electrically connected to the gate of the first transistor, one of a source of the second transistor and a drain of the second transistor is electrically connected to a high potential line, another one of the source of the second transistor and the drain of the second transistor is electrically connected to the first node, and the second transistor is a P-channel type thin film transistor; and
a third transistor, wherein a gate of the third transistor is electrically connected to another one of the source of the first transistor and the drain of the first transistor, one of a source of the third transistor and a drain of the third transistor is electrically connected to the low potential line, another one of the source of the third transistor and the drain of the third transistor is electrically connected to the first node, and the third transistor is a P-channel type thin film transistor.

### Claim 13 (depends on 12)

The gate drive circuit of claim 12, wherein a ratio of a width of a channel of the first transistor to a length of the channel of the first transistor is greater than 1.5, a ratio of a width of a channel of the second transistor to a length of the channel of the second transistor is in a range of 0.5-3, and a ratio of a width of a channel of the third transistor to a length of the channel of the third transistor is in a range of 0.5-3.

### Claim 14 (depends on 11)

The gate drive circuit of claim 11, wherein the pulse number reduction circuit comprises a fourth transistor, one of a source of the fourth transistor and a drain of the fourth transistor is electrically connected to the second node, another one of the source of the fourth transistor and the drain of the fourth transistor is electrically connected to the third node, and a gate of the fourth transistor is electrically connected to the reset line.

### Claim 15 (depends on 14)

The gate drive circuit of claim 14, wherein a ratio of a width of a channel of the fourth transistor to a length of the channel of the fourth transistor is greater than or equal to 0.5 and less than or equal to 1.5.

### Claim 16 (depends on 14)

The gate drive circuit of claim 14, wherein the pulse number reduction circuit further comprises a first capacitor, a terminal of the first capacitor is electrically connected to the gate of the fourth transistor, and another terminal of the first capacitor is electrically connected to the another one of the source of the fourth transistor and the drain of the fourth transistor.

### Claim 17 (depends on 16)

The gate drive circuit of claim 16, wherein the first output stage comprises:
a pull-up transistor, wherein a gate of the pull-up transistor is electrically connected to the third node, one of a source of the pull-up transistor and a drain of the pull-up transistor is electrically connected to a second clock line, and another one of the source of the pull-up transistor and the drain of the pull-up transistor is configured to output the first gate control signal; and
a second capacitor, wherein a terminal of the second capacitor is electrically connected to the gate of the pull-up transistor and another terminal of the second capacitor is electrically connected to the another one of the source of the pull-up transistor and the drain of the pull-up transistor,
wherein a ratio of a capacity of the first capacitor to a capacity of the second capacitor is greater than or equal to 0.5.

### Claim 18 (depends on 11)

The gate drive circuit of claim 11, wherein the second output stage has an output terminal electrically connected to a second gate control line for transmitting the second gate control signal, the second gate control signal having a first positive pulse and a second positive pulse in sequence in one frame; and
the first output stage has an output terminal electrically connected to a first gate control line for transmitting the first gate control signal, the first gate control signal having a first negative pulse in one frame.

### Claim 19 (depends on 18)

The gate drive circuit of claim 18, wherein, in one frame, a period of duration of the second positive pulse is longer than a period of duration of the first negative pulse, and the period of duration of the first negative pulse is within the period of duration of the second positive pulse.

### Claim 20 (depends on 19)

The gate drive circuit of claim 19, wherein the pull-up control circuit has a control terminal electrically connected to a first clock line for transmitting the first clock signal, the first output stage is electrically connected to a second clock line for transmitting a second clock signal, and a difference between a phase of the first clock signal and a phase of the second clock signal is 180°; and
each of a falling edge of the second clock signal, a falling edge of the second positive pulse, and a rising edge of the first negative pulse is within a period of duration of a positive pulse of the first clock signal.