# US 12,008,938 B2 · Display device with clock control chip and data driving chip for adjusting a phase of clock signal output

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- Number: US 12,008,938 B2
- Document ID: US12008938B2
- Status: Granted
- Kind: B2
- Application number: 17/607,844
- Filed: 2021-09-27
- Published: 2024-01-25
- Granted: 2024-06-11
- Earliest claimed: 2021-09-06
- Assignees: Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Tcl China Star Optoelectronics Technology Co., Ltd.
- Inventors: Jinfeng Liu
- Web page: https://patentgrep.com/patent/US12008938B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 5/008: {Clock recovery}
- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display device is provided. The display device includes a clock control chip configured to transmit display signals and a data driving chip connected to the clock control chip. The data driving chip is configured to adjust a phase of the clock signal output by the data driving chip based on the display signal.

## Claims

### Claim 1

A display device comprising:
a clock control chip configured to transmit display signals; and
a data driving chip connected to the clock control chip, wherein the data driving chip is configured to adjust a phase of a clock signal output by the data driving chip based on the display signals,
wherein the data driving chip comprises a clock generation module, a frequency confirmation module, a code type detection module, and an output control module, the clock generation module is connected to the frequency confirmation module, and the clock generation module and the code type detection module are both connected to the output control module;
wherein the clock generation module is configured to generate an initial clock signal and comprises: a first clock output terminal, wherein the first clock output terminal is connected to the frequency confirmation module, and the clock generation module outputs the initial clock signal to the frequency confirmation module through the first clock output terminal; a second clock output terminal, wherein the second clock output terminal is connected to the output control module, and the clock generation module outputs the adjusted initial clock signal to the output control module through the second clock output terminal; and a feedback input terminal, wherein the feedback input terminal is connected to the frequency confirmation module, and the clock generation module receives the feedback signal through the feedback input terminal;
wherein the frequency confirmation module is configured to receive the display signal and the initial clock signal, and output a feedback signal to the clock generation module based on the display signal and the initial clock signal to control the clock generation module to adjust frequency of the initial clock signal and to output an adjusted initial clock signal to the output control module, and comprises: a first frequency confirmation input terminal, wherein the first frequency confirmation input terminal is connected to the clock generation module, and the frequency confirmation module receives the initial clock signal through the first frequency confirmation input terminal; a second frequency confirmation input terminal, wherein the second frequency confirmation input terminal is connected to the clock control chip, and the frequency confirmation module receives the display signal through the second frequency confirmation input terminal; and a feedback output terminal wherein the feedback output terminal is connected to the clock generation module, and the frequency confirmation module outputs the feedback signal through the feedback output terminal;
wherein the code type detection module is configured to receive the display signal, obtain phase alignment starting point information based on the display signal, and output the phase alignment starting point information to the output control module, and comprises: a code type confirmation input terminal, wherein the code type confirmation input terminal is connected to the clock control chip, and the code type detection module receives the display signal through the code type confirmation input terminal; and a code type confirmation output terminal, wherein the code type confirmation output terminal is connected to the output control module, and the code type detection module outputs the phase alignment starting point information through the code type confirmation output terminal; and
wherein the output control module is configured to output the clock signal based on the adjusted initial clock signal and the phase alignment starting point information, and comprises: a first input terminal, wherein the first input terminal is connected to the clock generation module, and the output control module receives the adjusted initial clock signal through the first input terminal; a second input terminal, wherein the second input terminal is connected to the code type detection module, and the output control module receives the phase alignment starting point information through the second input terminal; and an output terminal, wherein the output control module outputs the clock signal through the output terminal.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the phase alignment starting point information comprises a rising edge starting point or a falling edge starting point.

### Claim 3 (depends on 2)

The display device of claim 2, wherein when the output control module receives the rising edge starting point or the falling edge starting point, the output control module resets the adjusted initial clock signal to obtain the clock signal.

### Claim 4 (depends on 1)

The display device of claim 1, wherein the driving chip further comprises a filter module, the filter module is connected to the clock generation module and the frequency confirmation module, and the filter module is configured to perform filter processing to the feedback signal.

### Claim 5 (depends on 4)

The display device of claim 4, wherein the filter module comprises a filter input terminal and a filter output terminal;
the filter input terminal is connected to the frequency confirmation module, and the filter module receives the feedback signal through the filter input terminal; and
the filter output terminal is connected to the output control module, and the filter module outputs a filtered feedback signal through the filter output terminal.

### Claim 6

A display device, comprising:
a clock control chip configured to transmit display signals; and
a data driving chip connected to the clock control chip, wherein the data driving chip is configured to adjust a phase of a clock signal output by the data driving chip based on the display signals;
the data driving chip comprises a clock generation module, a frequency confirmation module, a code type detection module, and an output control module, the clock generation module is connected to the frequency confirmation module, and the clock generation module and the code type detection module are both connected to the output control module;
wherein the clock generation module is configured to generate an initial clock signal, and comprises: a first clock output terminal, wherein the first clock output terminal is connected to the frequency confirmation module, and the clock generation module outputs the initial clock signal to the frequency confirmation module through the first clock output terminal; a second clock output terminal, wherein the second clock output terminal is connected to the output control module, and the clock generation module outputs the adjusted initial clock signal to the output control module through the second clock output terminal; and a feedback input terminal, wherein the feedback input terminal is connected to the frequency confirmation module, and the clock generation module receives the feedback signal through the feedback input terminal;
wherein the frequency confirmation module is configured to receive the display signal and the initial clock signal, and output a feedback signal to the clock generation module based on the display signal and the initial clock signal to control the clock generation module to adjust frequency of the initial clock signal and to output an adjusted initial clock signal to the output control module, and comprises: a first frequency confirmation input terminal, wherein the first frequency confirmation input terminal is connected to the clock generation module, and the frequency confirmation module receives the initial clock signal through the first frequency confirmation input terminal; a second frequency confirmation input terminal, wherein the second frequency confirmation input terminal is connected to the clock control chip, and the frequency confirmation module receives the display signal through the second frequency confirmation input terminal; and a feedback output terminal wherein the feedback output terminal is connected to the clock generation module, and the frequency confirmation module outputs the feedback signal through the feedback output terminal;
wherein the code type detection module is configured to receive the display signal, obtain phase alignment starting point information based on the display signal, and output the phase alignment starting point information to the output control module, and comprises: a code type confirmation input terminal, wherein the code type confirmation input terminal is connected to the clock control chip, and the code type detection module receives the display signal through the code type confirmation input terminal; and a code type confirmation output terminal, wherein the code type confirmation output terminal is connected to the output control module, and the code type detection module outputs the phase alignment starting point information through the code type confirmation output terminal;
wherein the output control module is configured to output the clock signal based on the adjusted initial clock signal and the phase alignment starting point information, and comprises: a first input terminal, wherein the first input terminal is connected to the clock generation module, and the output control module receives the adjusted initial clock signal through the first input terminal; a second input terminal, wherein the second input terminal is connected to the code type detection module, and the output control module receives the phase alignment starting point information through the second input terminal; and an output terminal, wherein the output control module outputs the clock signal through the output terminal; and
wherein the phase alignment starting point information comprises a rising edge starting point or a falling edge starting point.

### Claim 7 (depends on 6)

The display device of claim 6, wherein when the output control module receives the rising edge starting point or the falling edge starting point, the output control module resets the adjusted initial clock signal to obtain the clock signal.

### Claim 8 (depends on 6)

The display device of claim 6, wherein the driving chip further comprises a filter module, the filter module is connected to the clock generation module and the frequency confirmation module, and the filter module is configured to perform filter processing to the feedback signal.

### Claim 9 (depends on 8)

The display device of claim 8, wherein the filter module comprises a filter input terminal and a filter output terminal;
the filter input terminal is connected to the frequency confirmation module, and the filter module receives the feedback signal through the filter input terminal; and
the filter output terminal is connected to the output control module, and the filter module outputs a filtered feedback signal through the filter output terminal.