# US 12,008,417 B2 · Interconnect-based resource allocation for reconfigurable processors

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- Number: US 12,008,417 B2
- Document ID: US12008417B2
- Status: Granted
- Kind: B2
- Application number: 17/528,081
- Filed: 2021-11-16
- Published: 2022-09-29
- Granted: 2024-06-11
- Earliest claimed: 2021-03-26
- Assignees: SambaNova Systems, Inc.
- Applicants: SambaNova Systems, Inc.
- Inventors: Raghunath Shenbagam; Ravinder Kumar
- Web page: https://patentgrep.com/patent/US12008417B2

## CPC

- H04L 47/28: in relation to timing considerations
- G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals}
- G06F 9/5044: {considering hardware capabilities}
- G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)}
- G06F 15/7892: {Reconfigurable logic embedded in CPU, e.g. reconfigurable unit}
- G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
- G06N 3/0455: Auto-encoder networks; Encoder-decoder networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/063: using electronic means
- G06N 3/08: Learning methods
- G06N 3/09: Supervised learning
- G06N 3/098: Distributed learning, e.g. federated learning
- H04L 41/0816: the condition being an adaptation, e.g. in response to network events
- H04L 41/0843: {based on generic templates}
- H04L 41/0896: Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities (flow or congestion control using dynamic resource allocation, e.g. in-call renegotiation, H04L47/76)
- H04L 49/10: characterised by the switching fabric construction
- G06F 15/7867: {with reconfigurable architecture}
- G06F 2009/4557: {Distribution of virtual machine instances; Migration and load balancing}
- G06F 2009/45595: {Network integration; Enabling network access in virtual machine instances}
- G06F 2209/5011: Pool
- G06F 2213/0062: Bandwidth consumption reduction during transfers
- G06F 2213/0064: Latency reduction in handling transfers
- H04L 41/0895: Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
- H04L 45/121: by minimising delays
- H04L 45/745: Address table lookup; Address filtering
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

The technology disclosed relates to interconnect-based resource allocation for reconfigurable processors. In particular, the technology disclosed relates to a runtime logic that is configured to receive target interconnect bandwidth and target interconnect latency, and rated interconnect bandwidth and rated interconnect latency. The runtime logic is further configured to respond by allocating, to configuration files defining an application graph, processing elements in a plurality of processing elements, and interconnects between the processing elements, and executing the configuration files using the allocated processing elements and the allocated interconnects.

## Claims

### Claim 1

A data processing system, comprising:
a pool of reconfigurable dataflow resources, reconfigurable dataflow resources in the pool of reconfigurable dataflow resources including a plurality of reconfigurable processors operatively coupled by links, and the links having rated link bandwidths and rated link latencies; and
runtime logic operatively coupled to the pool of reconfigurable dataflow resources, and configured to:
receive, for a first application,
a first plurality of configuration files,
a first configuration of a first plurality of virtual reconfigurable processors required to execute the first application, and virtual links between virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, and
a first specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors;
allocate reconfigurable processors in the plurality of reconfigurable processors to the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, and links between the reconfigurable processors to the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors based on
a link bandwidth comparison that compares the target link bandwidths, specified by the first specification, against the rated link bandwidths, and
a link latency comparison that compares the target link latencies, specified by the first specification, against the rated link latencies; and
configure the allocated reconfigurable processors and the allocated links with configuration data in the first plurality of configuration files, and execute the first application using the configured reconfigurable processors and the configured links.