# US 12,008,401 B2 · Automatic central processing unit (CPU) usage optimization

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- Number: US 12,008,401 B2
- Document ID: US12008401B2
- Status: Granted
- Kind: B2
- Application number: 16/723,427
- Filed: 2019-12-20
- Published: 2021-06-24
- Granted: 2024-06-11
- Earliest claimed: 2019-12-20
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Anil Harwani; Amitabh Mehra; William R. Alverson; Grant E. Ley; Jerry A. Ahrens; Kenneth Mitchell
- Web page: https://patentgrep.com/patent/US12008401B2

## CPC

- G06F 9/5005: {to service a request}
- G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0656: {Data buffering arrangements}
- G06F 9/48: Program initiating; Program switching, e.g. by interrupt
- G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU]
- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 9/5088: {involving task migration}
- G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)}
- G06F 9/54: Interprogram communication
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 11/3433: {for load management (allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029)}
- G06F 2209/501: Performance criteria
- G06F 2209/5018: Thread allocation
- G06F 2209/502: Proximity
- G06F 2209/508: Monitor
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Automatic central processing unit (CPU) usage optimization includes: monitoring performance activity of a workload comprising a plurality of threads; and modifying a resource allocation of a plurality of cores for the plurality of threads based on the performance activity.

## Claims

### Claim 1

A method of automatic central processing unit (CPU) usage optimization, the CPU including a plurality of cores, the method comprising:
modifying a resource allocation of the plurality of cores for a plurality of threads based on performance activity of a workload comprising the plurality of threads; and
storing data, associated with the workload, indicating the modified resource allocation of the plurality of cores of the CPU, wherein the data indicating the modified resource allocation of the plurality of cores of the CPU is loaded upon a request for execution of the workload and the modified resource allocation is applied to the plurality of cores after the data is loaded.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
identifying, based on the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread;
wherein modifying the resource allocation comprises modifying a core assignment to reduce a physical distance between a first core of the plurality of cores assigned the first thread and a second core of the plurality of cores assigned the second thread.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first core and the second core are located within a same compute core complex (CCX), a same core complex die (CCD), a same socket, a same non-uniform memory access (NUMA) domain, and/or a same compute node.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
identifying, based on a degree of cache misses indicated in the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads assigned to a same core of the plurality of cores;
wherein modifying the resource allocation comprises assigning one or more of the first thread and the second thread to different cores of the plurality of cores.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
monitoring, after modifying the resource allocation, additional performance activity; and
determining, based on the additional performance activity, whether to undo a modification to the resource allocation.

### Claim 6 (depends on 1)

The method of claim 1, wherein modifying the resource allocation comprises modifying, for one or more cores of the plurality of cores, one or more thresholds based on the thread each respective core of the one or more cores is executing, wherein the one or more thresholds comprise a package power tracking (PPT) threshold, a thermal design current (TDC) threshold, an electrical design current (EDC) threshold, or a Reliability Limit comprising a threshold amount of time a core can safely spend at a voltage/temperature pair.

### Claim 7 (depends on 1)

The method of claim 1, wherein the data is stored in remote memory.

### Claim 8

An apparatus for automatic central processing unit (CPU) usage optimization, the apparatus comprising:
a CPU including a plurality of cores; and
memory operatively coupled to the CPU, stored within memory computer program instructions executed to:
modify a resource allocation of the plurality of cores for a plurality of threads based on performance activity of a workload comprising the plurality of threads; and
store data, associated with the workload, indicating the modified resource allocation of the plurality of cores of the CPU, wherein the data indicating the modified resource allocation of the plurality of cores of the CPU is loaded upon a request for execution of the workload and the modified resource allocation is applied to the plurality of cores after the data is loaded.

### Claim 9 (depends on 8)

The apparatus of claim 8, further comprising computer program instructions executed to:
identify, based on the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread;
wherein modifying the resource allocation comprises modifying a core assignment to reduce a physical distance between a first core of the plurality of cores assigned the first thread and a second core of the plurality of cores assigned the second thread.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the first core and the second core are located within a same compute core complex (CCX), a same core complex die (CCD), a same socket, a same non-uniform memory access (NUMA) domain, and/or a same compute node.

### Claim 11 (depends on 8)

The apparatus of claim 8, further comprising computer program instructions executed to:
identify, based on a degree of cache misses indicated in the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads assigned to a same core of the plurality of cores;
wherein modifying the resource allocation comprises assigning one or more of the first thread and the second thread to different cores of the plurality of cores.

### Claim 12 (depends on 8)

The apparatus of claim 8, further comprising computer program instructions executed to:
monitor, after modifying the resource allocation, additional performance activity; and
determine, based on the additional performance activity, whether to undo a modification to the resource allocation.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein the resource allocation is modified by modifying, for one or more cores of the plurality of cores, one or more thresholds based on the thread each respective core of the one or more cores is executing, wherein the one or more thresholds comprise a package power tracking (PPT) threshold, a thermal design current (TDC) threshold, an electrical design current (EDC) threshold, or a Reliability Limit comprising a threshold amount of time a core can safely spend at a voltage/temperature pair.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the data is stored in remote memory.

### Claim 15

A computer program product for automatic central processing unit (CPU) usage optimization, the CPU including a plurality of cores, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to:
modify a resource allocation of the plurality of cores for a plurality of threads based on performance activity of a workload comprising the plurality of threads; and
store data, associated with the workload, indicating the modified resource allocation of the plurality of cores of the CPU, wherein the data indicating the modified resource allocation of the plurality of cores of the CPU is loaded upon a request for execution of the workload and the modified resource allocation is applied to the plurality of cores after the data is loaded.

### Claim 16 (depends on 15)

The computer program product of claim 15, further comprising computer program instruction that, when executed, cause the computer to:
identify, based on the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread;
wherein the resource allocation is modified by modifying a core assignment to reduce a physical distance between a first core of the plurality of cores assigned the first thread and a second core of the plurality of cores assigned the second thread.

### Claim 17 (depends on 16)

The computer program product of claim 16, wherein the first core and the second core are located within a same compute core complex (CCX), a same core complex die (CCD), a same socket, a same non-uniform memory access (NUMA) domain, and/or a same compute node.

### Claim 18 (depends on 15)

The computer program product of claim 15, further comprising computer program instructions that, when executed, cause the computer to:
identify, based on a degree of cache misses indicated in the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads assigned to a same core of the plurality of cores;
wherein the resource allocation is modified by assigning one or more of the first thread and the second thread to different cores of the plurality of cores.

### Claim 19 (depends on 15)

The computer program product of claim 15, further comprising computer program instructions that, when executed, cause the computer to:
monitor, after modifying the resource allocation, additional performance activity; and
determine, based on the additional performance activity, whether to undo a modification to the resource allocation.

### Claim 20 (depends on 15)

The computer program product of claim 15, wherein the data is stored in remote memory.