Branch target buffer that stores predicted set index and predicted way number of instruction cache

A method, comprising:

• in a microprocessor that includes a branch target buffer (BTB) comprising a plurality of entries, wherein each entry is configured to hold:
• a tag that is based on at least a portion of a virtual address of a block of instructions previously fetched from a physically-indexed physically-tagged set associative instruction cache using a physical address that is a translation of the virtual address;
• a translated address bit portion of a set index of an entry of the instruction cache from which the block of instructions was previously fetched;
• and
• a way number of the entry of the instruction cache from which the block of instructions was previously fetched:
• in response to a hit on an entry of the plurality of entries of the BTB based on a fetch virtual address:
• providing, by the BTB, a translated address bit portion of a predicted set index that is the translated address bit portion of the set index from the hit entry of the BTB;
• and
• providing, by the BTB, a predicted way number that is the way number from the hit entry of the BTB;
• wherein the block of instructions comprises a sequential run of instructions;
• wherein each entry of the BTB is further configured to hold:
• a length of the sequential run of instructions;
• and
• a termination type of the sequential run of instructions, wherein the termination type specifies a reason for termination of the sequential run of instructions, wherein the reason includes a presence of a branch instruction that terminates the block of instructions or that the block of instructions continues sequentially into a next block of instructions;
• and
• wherein in response to the hit on the entry of the plurality of entries of the BTB based on the fetch virtual address, further:
• providing, by the BTB, a length that is the length from the hit entry of the BTB;
• and
• providing, by the BTB, a termination type that is the termination type from the hit entry of the BTB.

A non-transitory computer-readable medium having instructions stored thereon that are capable configuring a microprocessor comprising:

• a branch target buffer (BTB) comprising a plurality of entries, wherein each entry is configured to hold:
• a tag that is based on at least a portion of a virtual address of a block of instructions previously fetched from a physically-indexed physically-tagged set associative instruction cache using a physical address that is a translation of the virtual address;
• a translated address bit portion of a set index of an entry of the instruction cache from which the block of instructions was previously fetched;
• and
• a way number of the entry of the instruction cache from which the block of instructions was previously fetched;
• wherein in response to a hit on an entry of the plurality of entries of the BTB based on a fetch virtual address, the BTB is configured to provide:
• a translated address bit portion of a predicted set index that is the translated address bit portion of the set index from the hit entry of the BTB;
• and
• a predicted way number that is the way number from the hit entry of the BTB;
• wherein the block of instructions comprises a sequential run of instructions;
• wherein each entry of the BTB is further configured to hold:
• a length of the sequential run of instructions;
• and
• a termination type of the sequential run of instructions, wherein the termination type specifies a reason for termination of the sequential run of instructions, wherein the reason includes a presence of a branch instruction that terminates the block of instructions or that the block of instructions continues sequentially into a next block of instructions;
• and
• wherein in response to the hit on the entry of the plurality of entries of the BTB based on the fetch virtual address, the BTB is further configured to provide:
• a length that is the length from the hit entry of the BTB;
• and
• a termination type that is the termination type from the hit entry of the BTB.