# US 12,008,371 B2 · Method and apparatus for efficient programmable instructions in computer systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,371 B2 - Document ID: US12008371B2 - Status: Granted - Kind: B2 - Application number: 17/886,855 - Filed: 2022-08-12 - Published: 2022-12-01 - Granted: 2024-06-11 - Earliest claimed: 2019-06-25 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Andrew G. Kegel - Web page: https://patentgrep.com/patent/US12008371B2 ## CPC - G06F 9/30123: {according to context, e.g. thread buffers} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30079: {Pipeline control instructions, e.g. multicycle NOP} - G06F 9/48: Program initiating; Program switching, e.g. by interrupt - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 15/7871: {Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS} - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution. The results of other instructions, such as integer and floating point instructions, are available immediately to instructions executing on the reprogrammable execution unit since the reprogrammable execution unit shares the processor registers with the integer and floating point execution units. ## Claims ### Claim 1 A processor comprising: a dispatch unit comprising circuitry configured to store a first mapping that maps a first type of instruction to a first programmable execution unit and a second type of instruction to a second programmable execution unit; and wherein the processor comprises circuitry configured to: program the first programmable execution unit to execute the first type of instruction, responsive to a first program including more than a threshold number of instructions of the first type; program the second programmable execution unit to execute the second type of instruction; program the dispatch unit with the first mapping, responsive to detecting execution of a first program; and program the dispatch unit with a second mapping different from the first mapping. ### Claim 2 (depends on 1) The processor as recited in claim 1, wherein the processor is further configured to deactivate the first programmable execution unit responsive to detecting a context switch to a second program. ### Claim 3 (depends on 1) The processor as recited in claim 1, wherein the processor is further configured to program the first programmable execution unit to execute the first type of instruction, responsive to loading a first program comprising specialized instructions of the first type. ### Claim 4 (depends on 3) The processor as recited in claim 3, wherein the processor is configured to program the first programmable execution unit using a first bitfile associated with the first program. ### Claim 5 (depends on 4) The processor as recited in claim 4, the processor is configured to: detect an instruction which writes a first address to a first control register; and write the first address to the first control register, wherein the first address indicates a location in memory storing the first bitfile. ### Claim 6 (depends on 1) The processor as recited in claim 1, wherein the processor is configured to program the dispatch unit with the second mapping different from the first mapping, responsive to detecting at least one of a context switch to a second program or execution of the second program. ### Claim 7 (depends on 6) The processor as recited in claim 6, wherein the threshold number of instructions is based on a comparison of a number of instructions of the first type to executable instructions in the first program. ### Claim 8 A method comprising: storing a first mapping that maps a first type of instruction to a first programmable execution unit and a second type of instruction to a second programmable execution unit; programming the first programmable execution unit to execute the first type of instruction, responsive to a first program including more than a threshold number of instructions of the first type; programming the second programmable execution unit to execute the second type of instruction; programming a dispatch unit with the first mapping, responsive to detecting execution of a first program; and programming the dispatch unit with a second mapping different from the first mapping, responsive to detecting the first program is no longer being executed. ### Claim 9 (depends on 8) The method recited in claim 8, further comprising deactivating the first programmable execution unit responsive to detecting a context switch to a second program. ### Claim 10 (depends on 9) The method as recited in claim 9, further comprising programming the first programmable execution unit to execute the first type of instruction, responsive to loading a first program comprising specialized instructions of the first type. ### Claim 11 (depends on 10) The method as recited in claim 10, further comprising programming the first programmable execution unit using a first bitfile associated with the first program. ### Claim 12 (depends on 11) The method as recited in claim 11, further comprising: detecting an instruction which writes a first address to a first control register; and writing the first address to the first control register, wherein the first address indicates a location in memory storing the first bitfile. ### Claim 13 (depends on 8) The method as recited in claim 8, further comprising programming the dispatch unit with the second mapping different from the first mapping, responsive to detecting at least one of a context switch to a second program or execution of the second program. ### Claim 14 (depends on 13) The method as recited in claim 13, wherein the threshold number of instructions is based on a comparison of a number of instructions of the first type to executable instructions in the first program. ### Claim 15 A system comprising: a memory configured to store program instructions; and at least one processor coupled to the memory, wherein a first processor is comprises circuitry configured to: store a first mapping that maps a first type of instruction to a first programmable execution unit and a second type of instruction to a second programmable execution unit; and program the first programmable execution unit to execute the first type of instruction, responsive to a first program including more than a threshold number of instructions of the first type; program the second programmable execution unit to execute the second type of instruction; program a dispatch unit with the first mapping, responsive to execution of a first program; and program the dispatch unit with a second mapping different from the first mapping. ### Claim 16 (depends on 15) The system as recited in claim 15, wherein the first processor is further configured to: detect an instruction which writes a first address to a first control register; and write the first address to the first control register, wherein the first address indicates a location in the memory storing a first bitfile. ### Claim 17 (depends on 16) The system as recited in claim 16, wherein the first processor is configured to program the first programmable execution unit using the first bitfile. ### Claim 18 (depends on 17) The system as recited in claim 17, wherein the first bitfile is part of a first program. ### Claim 19 (depends on 17) The system as recited in claim 17, wherein the first processor is configured to program the first programmable execution unit using the first bitfile, responsive to loading the first program. ### Claim 20 (depends on 19) The system as recited in claim 19, wherein the first processor is configured to deactivate the first programmable execution unit responsive to detecting a context switch to a second program.