# US 12,008,367 B2 · Systems and methods for performing 16-bit floating-point vector dot product instructions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,367 B2 - Document ID: US12008367B2 - Status: Granted - Kind: B2 - Application number: 17/845,103 - Filed: 2022-06-21 - Published: 2022-10-13 - Granted: 2024-06-11 - Earliest claimed: 2018-11-09 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Alexander F. Heinecke; Robert Valentine; Mark J. Charney; Raanan Sade; Menachem Adelman; Zeev Sperber; Amit Gradstein; Simon Rubanovich - Web page: https://patentgrep.com/patent/US12008367B2 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30014: {with variable precision} - G06F 9/30038: {using a mask} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/3802: {Instruction prefetching} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed embodiments relate to systems and methods for performing 16-bit floating-point vector dot product instructions. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of 16-bit floating-point formatted elements of the specified first and second sources, and accumulate the resulting products with previous contents of a corresponding single-precision element of the specified destination, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode. ## Claims ### Claim 1 A processor comprising: fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of elements of the specified first and second sources having a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, and accumulate resulting products with previous contents of a corresponding element of the specified destination; decode circuitry to decode the fetched instruction; and the execution circuitry to respond to the decoded instruction as specified by the opcode. ### Claim 2 (depends on 1) The processor of claim 1, wherein the locations of each of the specified source and destination vectors are either in registers or in memory. ### Claim 3 (depends on 1) The processor of claim 1, wherein N is specified by the single instruction and has a value of one of 4, 8, 16, and 32. ### Claim 4 (depends on 1) The processor of claim 1, wherein the execution circuitry is to perform the multiplications without saturation and to saturate the result of the accumulation to plus or minus infinity in case of an overflow and to zero in case of any underflow. ### Claim 5 (depends on 1) The processor of claim 1, wherein the 16-bit floating-point format is bfloat16. ### Claim 6 (depends on 1) The processor of claim 1, wherein the execution circuitry is to generate all N elements of the specified destination in parallel. ### Claim 7 A method comprising: fetching, using fetch circuitry, a single instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of elements of the specified first and second sources having a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, and accumulate resulting products with previous contents of a corresponding element of the specified destination; decoding, using decode circuitry, the fetched instruction; and responding to the decoded instruction as specified by the opcode with the execution circuitry. ### Claim 8 (depends on 7) The method of claim 7, wherein the locations of each of the specified source and destination vectors are either in registers or in memory. ### Claim 9 (depends on 7) The method of claim 7, wherein N is specified by the single instruction and has a value of one of 4, 8, 16, and 32. ### Claim 10 (depends on 7) The method of claim 7, wherein the execution circuitry is to perform the multiplications without saturation and to saturate the result of the accumulation to plus or minus infinity in case of an overflow and to zero in case of any underflow. ### Claim 11 (depends on 7) The method of claim 7, wherein the 16-bit floating-point format is bfloat16. ### Claim 12 (depends on 7) The method of claim 7, wherein the execution circuitry is to generate all N elements of the specified destination in parallel. ### Claim 13 A system comprising: a memory; and a processor coupled to the memory, the processor comprising: fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of elements of the specified first and second sources having a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, and accumulate resulting products with previous contents of a corresponding element of the specified destination; decode circuitry to decode the fetched instruction; and the execution circuitry to respond to the decoded instruction as specified by the opcode. ### Claim 14 (depends on 13) The system of claim 13, wherein the locations of each of the specified source and destination vectors are either in registers in the processor or in the memory. ### Claim 15 (depends on 13) The system of claim 13, wherein the 16-bit floating-point format is bfloat16. ### Claim 16 (depends on 13) The system of claim 13, wherein the execution circuitry is to generate all N elements of the specified destination in parallel. ### Claim 17 A non-transitory machine-readable medium containing code to cause a processor to respond by: fetching, using fetch circuitry, a single instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate the processor is to multiply N pairs of elements of the specified first and second sources having a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, and accumulate resulting products with previous contents of a corresponding element of the specified destination; decoding, using decode circuitry, the fetched instruction; and responding to the decoded instruction as specified by the opcode with execution circuitry. ### Claim 18 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein the single instruction further includes a field to specify N, wherein N is an even number larger than 4. ### Claim 19 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein the execution circuitry is to perform the multiplications without saturation and to saturate the result of the accumulation to plus or minus infinity in case of an overflow and to zero in case of any underflow. ### Claim 20 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein the 16-bit floating-point format is bfloat16. ### Claim 21 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein the execution circuitry is to generate all N elements of the specified destination in parallel.