# US 12,008,361 B2 · Coherence-based dynamic code rewriting, tracing and code coverage

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- Number: US 12,008,361 B2
- Document ID: US12008361B2
- Status: Granted
- Kind: B2
- Application number: 17/531,582
- Filed: 2021-11-19
- Published: 2023-01-26
- Granted: 2024-06-11
- Earliest claimed: 2021-07-23
- Assignees: VMware, Inc.
- Applicants: VMware, Inc.
- Inventors: Irina Calciu; Andreas Nowatzyk; Pratap Subrahmanyam
- Web page: https://patentgrep.com/patent/US12008361B2

## CPC

- G06F 8/656: while running
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/3804: {for branches, e.g. hedging, branch folding}
- G06F 9/45533: {Hypervisors; Virtual machine monitors}
- G06F 13/1668: {Details of memory controller}
- G06F 11/3616: {using software metrics}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

## Claims

### Claim 1

A method of modifying a portion of code that is stored in code pages while the code is being executed in a processor, the method comprising:
prior to execution of the code by the processor, storing the code pages in a local memory of a device that is connected to the processor via a coherence interconnect; and
during execution of the code by the processor, monitoring by the device the coherence interconnect for requests to access cache lines of the code pages, wherein, in response to a request to read a cache line of the code pages having a particular address, the device retrieves the cache line of the code pages having the particular address from the local memory, stores the cache line retrieved from the local memory in a buffer, modifies the cache line stored in the buffer, and transmits the modified cache line to the processor in place of the cache line retrieved from the local memory.

### Claim 2 (depends on 1)

The method of claim 1, wherein contents of the modified cache line include a jump instruction to a patch code that is stored in the local memory of the device and contents of the cache line retrieved from the local memory do not.

### Claim 3 (depends on 1)

The method of claim 1, wherein contents of the modified cache line include a cache flush instruction and contents of the cache line retrieved from the local memory do not.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
recording each cache line of the code pages that has been accessed in the buffer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the code pages are code pages of an operating system kernel.

### Claim 6 (depends on 5)

The method of claim 5, wherein the operating system kernel is executing within a virtual machine.

### Claim 7 (depends on 5)

The method of claim 5, wherein the operating system kernel is executing within a physical machine.

### Claim 8

A non-transitory computer-readable medium comprising instructions to be executed in a device which is connected to a processor via a coherence interconnect, wherein the processor executes code having code pages that are stored in a local memory of the device and the instructions when executed in the device causes the device to carry out a method of modifying a portion of the code, the method comprising:
during execution of the code by the processor, monitoring the coherence interconnect for requests to access cache lines of code pages that are stored in the local memory of the device, and in response to a request to read a cache line of the code pages having a particular address, retrieving the cache line of the code pages having the particular address from the local memory, storing the cache line retrieved from the local memory in a buffer, modifying the cache line stored in the buffer, and transmitting the modified cache line to the processor in place of the cache line retrieved from the local memory.

### Claim 9 (depends on 8)

The non-transitory computer-readable medium of claim 8, wherein contents of the modified cache line include a jump instruction to a patch code that is stored in the local memory of the device and contents of the cache line retrieved from the local memory do not.

### Claim 10 (depends on 8)

The non-transitory computer-readable medium of claim 8, wherein contents of the modified cache line include a cache flush instruction and contents of the cache line retrieved from the local memory do not.

### Claim 11 (depends on 8)

The non-transitory computer-readable medium of claim 8, wherein the method further comprises:
recording each cache line of the code pages that has been accessed in the buffer.

### Claim 12 (depends on 8)

The non-transitory computer-readable medium of claim 8, wherein the code pages are code pages of an operating system kernel.

### Claim 13 (depends on 12)

The non-transitory computer-readable medium of claim 12, wherein the operating system kernel is executing within a virtual machine.

### Claim 14 (depends on 12)

The non-transitory computer-readable medium of claim 12, wherein the operating system kernel is executing within a physical machine.

### Claim 15

A computer system comprising
a processor;
a device connected to the processor via a coherence interconnect, the device including local memory in which code pages of code to be executed in the processor are stored, wherein the device is configured to:
during execution of the code by the processor, monitoring the coherence interconnect for requests to access cache lines of the code pages, and in response to a request to read a cache line of the code pages having a particular address, retrieving the cache line of the code pages having the particular address from the local memory, storing the cache line retrieved from the local memory in a buffer, modifying the cache line stored in the buffer, and transmitting the modified cache line to the processor in place of the cache line retrieved from the local memory.

### Claim 16 (depends on 15)

The computer system of claim 15, wherein contents of the modified cache line include a jump instruction to a patch code that is stored in the local memory of the device and contents of the cache line retrieved from the local memory do not.

### Claim 17 (depends on 15)

The computer system of claim 15, wherein contents of the modified cache line include a cache flush instruction and contents of the cache line retrieved from the local memory do not.

### Claim 18 (depends on 15)

The computer system of claim 15, wherein the device is further configured to:
record each cache line of the code pages that has been accessed in the buffer.

### Claim 19 (depends on 15)

The computer system of claim 15, wherein the code pages are code pages of an operating system kernel.

### Claim 20 (depends on 19)

The computer system of claim 19, wherein the operating system kernel is executing within a virtual machine or a physical machine.