# US 12,008,339 B2 · Pseudo-random permutation generator

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- Number: US 12,008,339 B2
- Document ID: US12008339B2
- Status: Granted
- Kind: B2
- Application number: 17/250,487
- Filed: 2019-07-31
- Published: 2021-09-23
- Granted: 2024-06-11
- Earliest claimed: 2018-08-03
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat à I'Energie Atomique et aux Energies Alternatives
- Inventors: Wissam Benjilali; William Guicquero
- Web page: https://patentgrep.com/patent/US12008339B2

## CPC

- G06F 7/582: {Pseudo-random number generators}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G06F 21/602: {Providing cryptographic facilities or services}
- G06F 21/72: in cryptographic circuits
- H03K 3/84: Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present description concerns a method of generation of a sequence of pseudo-random digital codes enabling to perform a permutation (3) of a first set of values (V) into a second set of values (Vp) based on said digital codes (CPos) representative of positions (j) of values (Vi) of the first set in the second set, including the steps of: generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number (W0) by application of a first function (24,26) from a seed number to the next seed number; applying a second function to each seed number of the chain to obtain each position code (CPos(j)), the second function including at least one permutation (PERM) followed by a bijection (BIJ).

## Claims

### Claim 1

Method of generation, on the fly, of a sequence of pseudo-random digital codes, comprising the steps of:
generating a first set of values from a first set of voltages;
generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number by application of a first function from a seed number to the next seed number;
applying a second function to each seed number of the chain of numbers to obtain a same number of position codes to provide digital codes, the second function comprising at least one first wired logic permutation followed by a bijection;
generating a second set of voltages from said digital codes, said digital codes representing respective positions of the values from the first set of voltages in the second set of voltages and allowing the performing, by a switching circuit, of a second permutation of the values from the first set of voltages in the second set of voltages.

### Claim 2

Method of compressive image acquisition from an array image sensor, comprising the steps of:
sequentially scanning rows of the array image sensor to perform, at each row, a parallel reading of information per column, each column delivering a voltage, wherein a first set of voltages delivered by the columns define a first set of values;
submitting the set of voltages delivered by the columns to a pseudo-random permutation performed by a switching circuit operatively connected to the array image sensor to deliver a second set of voltage values,
wherein the pseudo-random permutation is performed from digital codes representative of positions of the first set of values in the second set of voltage values, said digital codes being obtained by on the fly application of the steps of:
generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number by application of a first function from a seed number to the next seed number; and
applying a second function to each seed number of the chain of numbers to obtain a same number of position codes, the second function comprising at least a first permutation followed by a bijection, the pseudo-random permutation representing a second permutation.

### Claim 3 (depends on 1)

Method according to claim 1, wherein the first function is a function of iterative generation of the first wired logic permutation, the result of each iteration being applied to an input of the second function.

### Claim 4 (depends on 3)

Method according to claim 3, wherein the first function is an incrementation of an n-bit counter initialized by said initial pseudo-random seed number.

### Claim 5 (depends on 1)

Method according to claim 1, wherein the first function and the second function are one and the same, each position code being obtained by application of said first wired logic permutation followed by said bijection to the position code of previous rank.

### Claim 6 (depends on 5)

Method according to claim 5, further comprising, at each iteration, a test of the position code corresponding to a result of the second function at the previous rank to detect the presence of a code only comprising bits 0 or comprising a predetermined value, including at least one non-zero bit and preferably only bits at 1.

### Claim 7 (depends on 6)

Method according to claim 6, wherein, in the presence of a code only comprising bits 0, the seed number submitted to the first wired logic permutation of current rank is taken as equal to said predetermined value.

### Claim 8 (depends on 6)

Method according to claim 6, wherein, in the presence of a code comprising said predetermined value, the seed number submitted to the first wired logic permutation of current rank is taken as equal to a null code only comprising bits 0.

### Claim 9 (depends on 5)

Method according to claim 5, wherein said initial pseudo-random seed number is randomly selected.

### Claim 10 (depends on 1)

Method according to claim 1, wherein said bijection is a Gray code.

### Claim 11 (depends on 1)

Method according to claim 1, wherein each position code is a q-bit binary word, where q is equal to a base-2 logarithm of the number of values contained in each set of the first and second set of voltages.

### Claim 12 (depends on 1)

Method according to claim 1, wherein each seed number is coded with the same number of bits as the position codes.

### Claim 13 (depends on 1)

Method according to claim 1, wherein said first wired logic permutation performs a permutation of a number of least significant bits with the same number of most significant bits, this number of bits being:
one for a four- or fifteen bit-code;
two for a five-, eight-, nine-, or twelve-bit code;
three for a six-bit code;
one or two for a seven-bit code;
four or five for an eleven-bit code;
two or five for a thirteen-bit code;
four for a fourteen-bit code;
seven for a sixteen-bit code.

### Claim 14 (depends on 1)

Generator of a permutation of a first set of voltages into a second set of values, comprising, for each value of the second set of values, a selection circuit of a value of the first set of voltages according to a digital code and comprising a generation device of a sequence of pseudo-random digital codes implementing a generation method according to claim 1, the sequence of pseudo-random digital codes generated by said generation device being applied to the selection circuits and the sequence of pseudo-random digital codes representing the respective positions of the values of the first set of voltages in the second set of voltages.

### Claim 15 (depends on 14)

Generator according to claim 14, wherein each seed number of said chain of numbers is contained in a register.

### Claim 16 (depends on 15)

Generator according to claim 15, comprising, between each of said registers storing the seed numbers, a circuit capable of executing the first function of iterative generation of a permutation, wherein the first function is a function of iterative generation of the first wired logic permutation, the result of each iteration of the first function being applied to an input of the second function.

### Claim 17 (depends on 14)

Generator according to claim 14, wherein the generation device comprises, for each selection circuit, a generation circuit of a position code representative of the position of the value of the first set to be placed at the current position of the second set, said generation circuit being capable of executing the second function from the seed number associated with a current selection rank.

### Claim 18 (depends on 17)

Generator according to claim 17, wherein each generation circuit comprises a wired permutation circuit that only permutes a portion of bits submitted to the wired permutation circuit.

### Claim 19 (depends on 14)

Circuit of compressive sensing image processing, comprising at least one generator according to claim 14.

### Claim 20 (depends on 14)

Compressive sensing image sensor comprising a generator according to claim 14.