# US 12,008,337 B2 · Multi-input configurable logic cell with configurable output region > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,337 B2 - Document ID: US12008337B2 - Status: Granted - Kind: B2 - Application number: 17/474,859 - Filed: 2021-09-14 - Published: 2023-03-16 - Granted: 2024-06-11 - Earliest claimed: 2021-09-14 - Assignees: Oppstar Technology Sdn Bhd - Applicants: Oppstar Technology Sdn Bhd - Inventors: Kim Pin Tan; Kok Keong Liaw; Hun Wah Cheah - Web page: https://patentgrep.com/patent/US12008337B2 ## CPC - G06F 7/5318: {with column wise addition of partial products, e.g. using Wallace tree, Dadda counters (G06F7/5324 takes precedence)} - H03K 19/17724: Structural details of logic blocks - G06F 7/508: using carry look-ahead circuits - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables. ## Claims ### Claim 1 A configurable circuit, comprising: an input selection region, including a set of input multiplexers, that selects and routes input signals; a computation region that includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection region to generate a respective output signal; a switching region that includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals; and an output region that includes a domino logic stage, having a set of transistors, coupled to the output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables, wherein only one of the switching region or the output region is active for any given operation. ### Claim 2 (depends on 1) The configurable circuit of claim 1, wherein the input selection region includes four multiplexers that each receive two respective input signals and wherein the set of lookup tables includes four lookup tables. ### Claim 3 (depends on 2) The configurable circuit of claim 2, wherein the input selection region selects four signals from the input signals, A0, B0, C0, and D0, and provides the four signals to the four lookup tables during arithmetic operation, with A0 and B0 being provided as inputs to each of a first lookup table and a second lookup table of the four lookup tables and with C0 and D0 being provided as inputs to each of a third lookup table and a fourth lookup table. ### Claim 4 (depends on 3) The configurable circuit of claim 3, wherein the output region combines the signals output by the lookup tables with a carry signal to output a generate signal and a propagate signal. ### Claim 5 (depends on 4) The configurable circuit of claim 4, wherein the output region includes a set of transistors that are triggered by respective output signals of the four lookup tables and a carry bit transistor that is triggered by the carry signal. ### Claim 6 (depends on 2) The configurable circuit of claim 2, wherein the input selection region selects four signals from the input signals, A0, B0, C0, and D0, and provides the four signals to the four lookup tables during a six-input logic operation, with A0, B0, C0, and D0 being provided as inputs to each of the four lookup tables, and wherein the set of output multiplexers selects a circuit output from one of the four lookup tables in accordance with two select signal inputs. ### Claim 7 (depends on 2) The configurable circuit of claim 2, wherein the input selection region selects two distinct sets of input signals, including a first set, A1, B1, C0, and D0, and a second set, A0, B0, C1, and D1, and provides the first set as inputs to each of a first pair of lookup tables from the four lookup tables and provides the second set as inputs to a second pair of lookup tables from the four lookup tables, during split-cell operation, and wherein the set of output multiplexers selects a first output signal for the first pair of lookup tables and a second output signal for the second pair of lookup tables in accordance with a shared select signal input. ### Claim 8 (depends on 2) The configurable circuit of claim 2, wherein the input selection region selects two distinct sets of input signals, including a first set, A1, B1, C0, and D0, and a second set, A0, B0, C1, and D1, and provides the first set as inputs to a first lookup table from the four lookup tables and provides the second set as inputs to a second lookup table from the four lookup tables, during split-cell operation. ### Claim 9 (depends on 8) The configurable circuit of claim 8, wherein the output region generates a first circuit output signal from an output signal of the first lookup table and a second circuit output signal from an output signal of the second lookup table. ### Claim 10 (depends on 2) The configurable circuit of claim 2, wherein the input selection region selects two distinct sets of input signals, including a first set, A1, B1, C0, and D0, and a second set, A0, B0, C1, and D1, and provides the first set as inputs to a first lookup tables from the four lookup tables and provides the second set as inputs to each of a pair of lookup tables from the four lookup tables, during split-cell operation. ### Claim 11 (depends on 10) The configurable circuit of claim 10, wherein the output region combines the signals output by the pair of lookup tables with a carry signal to generate an output of a five-input logic operation. ### Claim 12 (depends on 2) The configurable circuit of claim 2, wherein the input selection region selects two distinct sets of input signals, including a first set, A1, B1, C0, and D0, and a second set, A0, B0, C1, and D1, and provides the first set as inputs to each of a first pair of lookup tables from the four lookup tables and provides the second set as inputs to a second pair of lookup tables from the four lookup tables, during a partial nine-input logic operation. ### Claim 13 (depends on 12) The configurable circuit of claim 12, wherein the output region combines the signals output by each of the four lookup tables with a carry signal to generate an output of the partial nine-input logic operation. ### Claim 14 (depends on 1) The configurable circuit of claim 1, wherein the configurable circuit is implemented in a single logic block of a field programmable gate array (FPGA). ### Claim 15 A multi-function configurable circuit, comprising: an input selection region, including a set of four input multiplexers, that selects and routes input signals; a computation region that includes a set of four four-input lookup tables, each lookup table being coupled to selected signals from the input selection region to generate a respective output signal, with the computation region being split to perform multiple logic operations; a switching region that includes a set of output multiplexers, each output multiplexer being coupled to a respective set of output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals; and an output region that includes a domino logic stage, having a set of transistors, coupled to the output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables, wherein only one of the switching region or the output region is active for any given operation. ### Claim 16 (depends on 15) The configurable circuit of claim 15, wherein each of the four four-input lookup tables receives inputs from two of the four input multiplexers. ### Claim 17 (depends on 15) The configurable circuit of claim 15, wherein the configurable circuit is implemented in a single logic block of a field programmable gate array (FPGA). ### Claim 18 A configurable circuit product, the configurable circuit product having a non-transitory machine-readable storage medium that stores circuit configuration instructions, the circuit configuration instructions being readable by a field programmable gate array device to initialize a circuit that comprises: an input selection region, including a set of input multiplexers, that selects and routes input signals; a computation region that includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection region to generate a respective output signal; a switching region that includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals; and an output region that includes a domino logic stage, having a set of transistors, coupled to the output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables, wherein only one of the switching region or the output region is active for any given operation. ### Claim 19 (depends on 18) The configurable circuit product of claim 18, wherein the input selection region includes four multiplexers that each receive two respective input signals and wherein the set of lookup tables includes four lookup tables. ### Claim 20 (depends on 18) The configurable circuit product of claim 18, wherein the configurable circuit is implemented in a single logic block of a field programmable gate array (FPGA).