# US 12,008,302 B2 · Integrated circuit with thicker metal lines on lower metallization layer

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- Number: US 12,008,302 B2
- Document ID: US12008302B2
- Status: Granted
- Kind: B2
- Application number: 18/173,731
- Filed: 2023-02-23
- Published: 2023-06-29
- Granted: 2024-06-11
- Earliest claimed: 2020-06-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuang-Hung Chang; Yuan-Te Hou; Chung-Hsing Wang; Yung-Chin Hou
- Web page: https://patentgrep.com/patent/US12008302B2

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10W 20/42: Vias, e.g. via plugs
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10D 84/834: {comprising FinFETs}
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- G06F 30/337: Design optimisation
- G06F 30/373: Design optimisation
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10D 30/62: Fin field-effect transistors [FinFET]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
a first net electrically connecting the first transistor and the second transistor, the first net comprising a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors; and
a second net electrically connecting the third transistor and the fourth transistor, the second net comprising a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors, wherein a count of the plurality of first metal vias of the first net is less than a count of the plurality of second metal vias of the second net, and a line height of each of the plurality of first metal lines of the first net is greater than a line height of each of the plurality of second metal lines of the second net.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein the second metallization layer is above the first metallization layer.

### Claim 3 (depends on 1)

The IC structure of claim 1, further comprising:
a plurality of third metal lines below the plurality of first metal lines, wherein a line height of each of the plurality of third metal lines is greater than the line height of each of the plurality of second metal lines of the second net.

### Claim 4 (depends on 3)

The IC structure of claim 3, wherein the line height of each of the plurality of third metal lines is equal to the line height of each of the plurality of first metal lines of the first net.

### Claim 5 (depends on 1)

The IC structure of claim 1, further comprising:
a plurality of fourth metal lines above the plurality of second metal liens, wherein a line height of each of the plurality of fourth metal lines is greater than the line height of each of the plurality of second metal lines of the second net.

### Claim 6 (depends on 5)

The IC structure of claim 5, wherein the line height of each of the plurality of fourth metal lines is equal to the line height of each of the plurality of first metal lines of the first net.

### Claim 7 (depends on 6)

The IC structure of claim 6, wherein a line width of each of the plurality of fourth metal lines is less than a line width of each of the plurality of first metal lines of the first net.

### Claim 8 (depends on 7)

The IC structure of claim 7, wherein the line width of each of the plurality of fourth metal lines is greater than a line width of each of the plurality of second metal lines of the second net.

### Claim 9

An IC structure, comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
a first net electrically connecting the first transistor and the second transistor, the first net comprising a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors; and
a second net electrically connecting the third transistor and the fourth transistor, the second net comprising a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors, wherein a count of the plurality of first metal vias of the first net is less than a count of the plurality of second metal vias of the second net, and a line-to-line spacing between adjacent two of the plurality of first metal lines of the first net is greater than a line-to-line spacing between adjacent two of the plurality of second metal lines of the second net.

### Claim 10 (depends on 9)

The IC structure of claim 9, further comprising:
a plurality of third metal lines below the plurality of first metal lines, wherein a line-to-line spacing between adjacent two of the plurality of third metal lines is less than the line-to-line spacing between adjacent two of the plurality of first metal lines of the first net.

### Claim 11 (depends on 10)

The IC structure of claim 10, wherein the line-to-line spacing between adjacent two of the plurality of third metal lines is greater than the line-to-line spacing between adjacent two of the plurality of second metal lines of the second net.

### Claim 12 (depends on 9)

The IC structure of claim 9, further comprising:
a plurality of fourth metal lines above the plurality of second metal lines, wherein a line-to-line spacing between adjacent two of the plurality of fourth metal lines is less than the line-to-line spacing between adjacent two of the plurality of first metal lines of the first net.

### Claim 13 (depends on 12)

The IC structure of claim 12, wherein the line-to-line spacing between adjacent two of the plurality of fourth metal lines is greater than the line-to-line spacing between adjacent two of the plurality of second metal lines of the second net.

### Claim 14 (depends on 12)

The IC structure of claim 12, wherein a line width of each of the plurality of fourth metal lines is less than a line width of the plurality of first metal lines of the first net.

### Claim 15 (depends on 14)

The IC structure of claim 14, wherein the line width of each of the plurality of fourth metal lines is greater than a line width of the plurality of second metal lines of the second net.

### Claim 16

An IC structure, comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
a first net electrically connecting the first transistor and the second transistor, the first net comprising a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors; and
a second net electrically connecting the third transistor and the fourth transistor, the second net comprising a plurality of second metal lines routed on a second metallization layer above the plurality of first metal lines, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors, wherein a count of the plurality of first metal vias of the first net is less than a count of the plurality of second metal vias of the second net, and a total length of the plurality of first metal lines of the first net is longer than a total length of the plurality of second metal lines of the second net.

### Claim 17 (depends on 16)

The IC structure of claim 16, wherein a line width of each of the plurality of first metal lines of the first net is greater than a line width of each of the plurality of second metal lines of the second net.

### Claim 18 (depends on 16)

The IC structure of claim 16, wherein a line height of each of the plurality of first metal lines of the first net is greater than a line height of each of the plurality of second metal lines of the second net.

### Claim 19 (depends on 16)

The IC structure of claim 16, wherein a distance between adjacent ones of the plurality of first metal lines of the first net is greater than a distance between adjacent ones of the plurality of second metal lines of the second net.

### Claim 20 (depends on 16)

The IC structure of claim 16, wherein the second metallization layer is a next layer to the first metallization layer.