# US 12,008,270 B2 · System, device, and method for memory interface including reconfigurable channel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,270 B2 - Document ID: US12008270B2 - Status: Granted - Kind: B2 - Application number: 17/994,077 - Filed: 2022-11-25 - Published: 2023-03-23 - Granted: 2024-06-11 - Earliest claimed: 2020-08-21 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Youngwook Kim - Web page: https://patentgrep.com/patent/US12008270B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 13/1684: {using multiple buses} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 13/161: {with latency improvement} - G06F 13/4243: {with synchronous protocol} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method of communicating with a memory device through a plurality of sub-channels and a control sub-channel includes; setting a first mode or a second mode. In the first mode, writing or reading first data corresponding to a command synchronized to the control sub-channel through the plurality of sub-channels, and in the second mode, independently writing or reading second data and third data respectively corresponding to different commands synchronized to the control sub-channel through the plurality of sub-channels. ## Claims ### Claim 1 A storage device comprising: a nonvolatile memory including a first region and a second region; and a controller coupled to the nonvolatile memory, wherein in a first mode, the controller is configured to perform a first operation by communicating with the first region of the nonvolatile memory via both a first sub-channel and a second sub-channel, in a second mode, the controller is configured to perform a second operation by communicating with the first region of the nonvolatile memory via the first sub-channel and to perform a third operation by communicating with the second region of the nonvolatile memory via the second sub-channel, the controller is configured to perform the second operation during a first time period and the third operation during a second time period, and a first time period is at least partially overlapped a second time period. ### Claim 2 (depends on 1) The storage device of claim 1, wherein each of the first operation and the second operation is a write operation, and the third operation is a read operation. ### Claim 3 (depends on 1) The storage device of claim 1, wherein the controller is configured to perform the second operation and the third operation at the same time. ### Claim 4 (depends on 1) The storage device of claim 1, wherein the controller selects one of the first mode and the second mode, based on a request received from an external device. ### Claim 5 (depends on 4) The storage device of claim 4, wherein the controller selects the first mode when multiple read requests are successively received or when multiple write requests are successively received. ### Claim 6 (depends on 4) The storage device of claim 4, wherein the controller selects the second mode when read requests and write requests are non-sequentially received. ### Claim 7 (depends on 1) The storage device of claim 1, further comprising: a first interface circuit connected to the nonvolatile memory through the first sub-channel; and a second interface circuit connected to the nonvolatile memory through the second sub-channel. ### Claim 8 A storage device comprising: a nonvolatile memory including a first region and a second region; and a controller coupled to the nonvolatile memory, and configured to select one of a first mode and a second mode based on a request received from an external device, wherein in the first mode, the controller is configured to perform a first operation by communicating with the nonvolatile memory via both a first channel and a second channel, in the second mode, the controller is configured to perform a second operation by communicating with the nonvolatile memory via the first channel and to perform a third operation by communicating with the nonvolatile memory via the second channel, the controller is configured to perform the second operation and the third operation, and the second operation is performed while the third operation is performed. ### Claim 9 (depends on 8) The storage device of claim 8, wherein in the first mode, the controller performs the first operation by communicating with the first region of the nonvolatile memory via both a first channel and a second channel, and in the second mode, the controller performs the second operation by communicating with the first region of the nonvolatile memory via the first channel and performs the third operation by communicating with the second region of the nonvolatile memory via the second channel. ### Claim 10 (depends on 8) The storage device of claim 8, wherein each of the first operation and the second operation is a write operation, and the third operation is a read operation. ### Claim 11 (depends on 8) The storage device of claim 8, wherein the controller is configured to perform the second operation and the third operation at the same time. ### Claim 12 (depends on 8) The storage device of claim 8, wherein the controller selects the first mode when multiple read requests are successively received or when multiple write requests are successively received. ### Claim 13 (depends on 8) The storage device of claim 8, wherein the controller selects the second mode when read requests and write requests are non-sequentially received. ### Claim 14 (depends on 8) The storage device of claim 8, further comprising: a first interface circuit connected to the nonvolatile memory through the first channel; a second interface circuit connected to the nonvolatile memory through the second channel; and a third interface circuit connected to the nonvolatile memory through a control channel through which the controller provides a control signal to the nonvolatile memory. ### Claim 15 A storage device comprising: a nonvolatile memory including a first region and a second region; and a controller coupled to the nonvolatile memory, and configured to select one of a first mode and a second mode, wherein in the first mode, the controller is configured to perform a first operation by communicating first data with the first region of the nonvolatile memory via both a first channel and a second channel, in the second mode, the controller is configured to perform a second operation by communicating second data with the first region of the nonvolatile memory via the first channel and to perform a third operation by communicating third data with the second region of the nonvolatile memory via the second channel, the controller is configured to provide a control signal to the nonvolatile memory via a third channel, the controller is configured to perform the second operation during a first time period and the third operation during a second time period, and a first time period is at least partially overlapped a second time period. ### Claim 16 (depends on 15) The storage device of claim 15, wherein each of the first operation and the second operation is a write operation, and the third operation is a read operation. ### Claim 17 (depends on 15) The storage device of claim 15, wherein the controller is configured to perform the second operation and the third operation at the same time. ### Claim 18 (depends on 15) The storage device of claim 15, wherein the controller selects one of the first mode and the second mode, based on a request received from an external device. ### Claim 19 (depends on 15) The storage device of claim 15, wherein the controller selects the first mode when multiple read requests are successively received or when multiple write requests are successively received, and the controller selects the second mode when read requests and write requests are non-sequentially received. ### Claim 20 (depends on 15) The storage device of claim 15, further comprising: a first interface circuit connected to the nonvolatile memory through the first channel; a second interface circuit connected to the nonvolatile memory through the second channel; and a third interface circuit connected to the nonvolatile memory through the third channel.