# US 12,008,268 B2 · Memory device including interface circuit and method of operating the same

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- Number: US 12,008,268 B2
- Document ID: US12008268B2
- Status: Granted
- Kind: B2
- Application number: 17/867,008
- Filed: 2022-07-18
- Published: 2022-11-03
- Granted: 2024-06-11
- Earliest claimed: 2019-10-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Daehoon Na; Jeongdon Ihm; Jangwoo Lee; Byunghoon Jeong
- Web page: https://patentgrep.com/patent/US12008268B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 3/0611: {in relation to response time}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

## Claims

### Claim 1

A memory system comprising:
a memory controller configured to transmit, to a host device, read data according to a first clock, in response to read command received from the host device; and
a memory device including,
a first NVM,
a second NVM, and
an interface circuit connected between the memory controller and the first NVM and the second NVM, the interface circuit configured to,
receive, from the memory controller, the first clock, and to generate and transmit, a second clock which is divided from the first clock based on a number of NVMs, to each of the first NVM and the second NVM,
receive, at a first time, a first data strobe signal generated by the first NVM,
receive, at a second time, a second data strobe signal generated by the second NVM,
identify a skew based on the first time and the second time,
identify a first time delay associated with outputting data from the first NVM and a second time delay associated with outputting data from the second NVM based on the skew, and
generate and transmit, to the memory controller, the read data by,
temporarily storing first divided read data received from the first NVM and second divided read data received from the second NVM in a first buffer register and a second buffer register, respectively,
outputting the first divided read data from the first NVM based on the first time delay and the second divided read data from the second NVM based on the second time delay,
combining the first divided read data that was output based on the first time delay and the second divided read data that was output based on the second time delay to generate the read data, and
transmitting the read data to the memory controller.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein, when the first time precedes the second time,
the first delay time includes the skew and a delay margin time, and
the second delay time includes the delay margin time.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the serializer is configured to concurrently receive the first divided read data from the first NVM and the second divided read data from the second NVM.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein
the first NVM is configured to transmit the first data strobe signal to the TDC, and transmit the first data strobe signal and the first divided read data to the first buffer register, and
wherein the second NVM is configured to transmit the second data strobe signal to the TDC, and transmit the second data strobe signal and the second divided read data to the second buffer register.

### Claim 5

A memory system comprising:
a memory controller configured to receive a first clock and a read command from a host device, transmit a first control signal or a second control signal to an interface circuit, transmit read data according to the first clock to the host device; and
a memory device including a first NVM, a second NVM, and the interface circuit which is connecting between the memory controller and the first NVM and the second NVM,
wherein the interface circuit is configured to:
in response to receiving the first control signal from the memory controller, generate and transmit, a second clock which is divided from the first clock based on a number of NVMs, to each of the first NVM and the second NVM,
in response to receiving the second control signal from the memory controller, transmit the first clock received from the memory controller to the first NVM and the second NVM,
receive, at a first time, a first data strobe signal generated by the first NVM,
receive, at a second time, a second data strobe signal generated by the second NVM,
identify a skew based on the first time and the second time, and
generate and transmit, to the memory controller, the read data by combining first divided read data from the first NVM and second divided read data from the second NVM based on the skew, and
wherein the memory controller is configured to transmit one of the first control signal and the second control signal, to the interface circuit, based on a value of the first clock.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the interface circuit further comprises a serializer including a first buffer register, a second buffer register, and a combiner, and
wherein the first buffer register corresponds to the first NVM, and the second buffer register corresponds to the second NVM.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the interface circuit further comprises a TDC (time to digital converter) configured to identify the skew,
wherein the skew is calculated by a time difference between the first time and the second time, and
wherein the interface circuit is further configured to calculate a first delay time for the first buffer register, and a second delay time for the second buffer register.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the interface circuit is further configured to:
delay outputting the first divided read data from the first buffer register to the serializer for the first delay time,
delay outputting the second divided read data from the second buffer register to the serializer for the second delay time, and
wherein the first delay time is different from the second delay time.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein, when the first time precedes the second time, the first delay time includes the skew and a delay margin time, and
wherein the second delay time includes the delay margin time.

### Claim 10 (depends on 8)

The memory system of claim 8, wherein the serializer is configured to concurrently receive the first divided read data from the first NVM and the second divided read data from the second NVM.

### Claim 11 (depends on 7)

The memory system of claim 7, wherein the first NVM is configured to transmit the first data strobe signal to the TDC, and transmit the first data strobe signal and the first divided read data to the first buffer register, and
wherein the second NVM is configured to transmit the second data strobe signal to the TDC, and transmit the second data strobe signal and the second divided read data to the second buffer register.

### Claim 12 (depends on 5)

The memory system of claim 5, wherein:
if a frequency of the first clock is close to a maximum operating frequency, the memory controller is configured to transmit the first control signal to the interface circuit, and
if a frequency of the first clock is not close to the maximum operating frequency, the memory controller is configured to transmit the second control signal to the interface circuit.

### Claim 13

An operating method of a memory device including a first NVM, a second NVM and an interface circuit connected to each of the first NVM and the second NVM, the method comprising:
receiving, by the interface circuit, a first clock signal;
in response to receiving a first control signal from a memory controller, generating and transmitting, by the interface circuit, a second clock signal, which is divided from the first clock signal based on a number of NVMs, to each of the first NVM and the second NVM;
in response to receiving a second control signal from the memory controller, transmitting, by the interface circuit, the first clock received from the memory controller to the first NVM and the second NVM;
receiving, by the interface circuit at a first time, a first data strobe signal generated by the first NVM in response to the first NVM receiving of the second clock signal from the interface circuit;
receiving, by the interface circuit at a second time, a second data strobe signal generated by the second NVM in response to the second NVM receiving of the second clock signal from the interface circuit;
identifying, by the interface circuit, a skew based on the first time and the second time; and
generating and transmitting, to the memory controller, read data by combining first divided read data from the first NVM and second divided read data from the second NVM based on the skew, and
wherein the interface circuit is configured to receive one of the first control signal and the second control signal from the memory controller based on a value of the first clock.

### Claim 14 (depends on 13)

The operating method of claim 13, further comprising:
transmitting, by the first NVM, the first divided read data to the interface circuit;
transmitting, by the second NVM, the second divided read data to the interface circuit;
generating, by the interface circuit, the read data based on the first divided read data and the second divided read data; and
outputting, by the interface circuit, the read data based on the first clock signal.

### Claim 15 (depends on 14)

The operating method of claim 14, wherein:
the first data strobe signal is transmitted based on the second clock signal,
the second data strobe signal is transmitted based on the second clock signal,
the first divided read data is transmitted based on the second clock signal, and
the second divided read data is transmitted based on the second clock signal.

### Claim 16 (depends on 14)

The operating method of claim 14, wherein the generating of the read data further comprises:
calculating, by the interface circuit, a first delay time for the first divided read data, based on the skew; and
calculating, by the interface circuit, a second delay time for the second divided read data, based on the skew,
wherein if the interface circuit receives the first data strobe signal faster than the second data strobe signal, the first delay time is greater than the second delay time.

### Claim 17 (depends on 16)

The operating method of claim 16, further comprising:
delaying, by the interface circuit, the first divided read data during the first delay time from a time the first divided read data is received by the interface circuit;
delaying, by the interface circuit, the second divided read data during the second delay time from a time the second divided read data is received by the interface circuit; and
combining the first divided read data and the second divided read data in response to elapse each of the first delay time and the second delay time.