# US 12,008,247 B2 · Memory system

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- Number: US 12,008,247 B2
- Document ID: US12008247B2
- Status: Granted
- Kind: B2
- Application number: 17/884,283
- Filed: 2022-08-09
- Published: 2023-07-06
- Granted: 2024-06-11
- Earliest claimed: 2022-01-05
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Takayuki Takano
- Web page: https://patentgrep.com/patent/US12008247B2

## CPC

- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- G06F 2212/1028: Power efficiency
- G06F 2212/7202: Allocation control and policies
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory system includes a nonvolatile memory and a controller that includes an encoder configured to encode a first group of data including a plurality of first data, each first data having a plurality of bits. The encoder is configured to perform a first encoding process of generating a second group of data including a plurality of second data from the plurality of first data in the first group, and a second encoding process of generating a third group of data including a plurality of third data from the plurality of second data in the second group. A logical value of “1” is less likely to be the value in an n-th bit position of the plurality of third data in the third group than the value in any of the bit positions of the plurality of second data in the second group.

## Claims

### Claim 1

A memory system comprising:
a nonvolatile memory;
a memory bus that includes a plurality of data lines; and
a controller that includes an encoder configured to encode a first group of data including a plurality of first data, each first data having a plurality of bits, and is configured to transmit the encoded first group of data to the nonvolatile memory via the data lines,
wherein the encoder is configured to perform a first encoding process of generating a second group of data including a plurality of second data from the plurality of first data in the first group, and a second encoding process of generating a third group of data including a plurality of third data from the plurality of second data in the second group, each of the second data and each of the third data having the same number of bits as the first data, and
in the first encoding process, for each first data in the first group:
if the number of bits of the first data having a first logical value is greater than or equal to the number of bits of the first data having a second logical value, each bit of the second data has the same logical value as a corresponding bit of the first data; and
if the number of bits of the first data having the first logical value is less than the number of bits of the first data having the second logical value, each bit of the second data has an inverted logical value of the corresponding bit of the first data, and
wherein the second logical value is less likely to be the value in an n-th bit position of the plurality of third data in the third group than the value in any of the bit positions of the plurality of second data in the second group.

### Claim 2 (depends on 1)

The memory system according to claim 1, wherein data written to the nonvolatile memory and each of the first data in the first group have randomized patterns.

### Claim 3 (depends on 1)

The memory system according to claim 1, wherein
the third group of data is the encoded first group of data, and
the controller is configured to transmit to the nonvolatile memory each of the third data in the third group over the data lines along with a flag that indicates whether or not the number of bits having the first logical value in the first data from which the third data was generated is less than the number of bits having the second logical value in the first data from which the third data was generated.

### Claim 4 (depends on 1)

The memory system according to claim 1, wherein
the nonvolatile memory includes memory cells in which data are stored and a decoder configured to convert each of the third data in the third group into a fourth data, which are stored in the memory cells.

### Claim 5 (depends on 1)

The memory system according to claim 1, wherein
the nonvolatile memory includes an encoder configured to perform a third encoding process on a fourth group of data including a plurality of fourth data read from memory cells of the nonvolatile memory, to generate a fifth group of data including a plurality of fifth data, and a fourth encoding process of generating a sixth group of data including a plurality of sixth data from the plurality of fifth data in the fifth group, and
in the third encoding process, for each fourth data in the fourth group:
if the number of bits of the fourth data having the first logical value is greater than or equal to the number of bits of the fourth data having the second logical value, each bit of the fifth data has the same logical value as a corresponding bit of the fourth data; and
if the number of bits of the fourth data having the first logical value is less than the number of bits of the fourth data having the second logical value, each bit of the fifth data has an inverted logical value of the corresponding bit of the fourth data, and
wherein the second logical value is less likely to be the value in an m-th bit position of the plurality of sixth data in the sixth group than the value in any of bit positions of the plurality of fifth data in the fifth group.

### Claim 6 (depends on 5)

The memory system according to claim 5, wherein
the nonvolatile memory is configured to transmit to the controller each of the sixth data in the sixth group over the data lines along with a flag that indicates whether or not the number of bits having the first logical value in the fourth data from which the sixth data was generated is less than the number of bits having the second logical value in the fourth data from which the sixth data was generated.

### Claim 7 (depends on 5)

The memory system according to claim 5, wherein
the controller includes a decoder configured to convert each of the sixth data in the sixth group into a seventh data, and output the seventh data.

### Claim 8 (depends on 7)

The memory system according to claim 7, wherein
the controller is configured to transmit the seventh data output from the decoder to a host.

### Claim 9 (depends on 5)

The memory system according to claim 5, wherein
the nonvolatile memory further includes a switching circuit configured to switch connections between the encoder of the nonvolatile memory and the memory bus, so that the m-th bit of the sixth data output by the encoder of the nonvolatile memory is connectable to a predetermined data line of the memory bus.

### Claim 10 (depends on 1)

The memory system according to claim 1, wherein
the controller further includes a switching circuit configured to switch connections between the encoder of the controller and the memory bus, so that the n-th bit of the third data output by the encoder of the controller is connectable to a predetermined data line of the memory bus.

### Claim 11 (depends on 1)

The memory system according to claim 1, wherein
each of the first data in the first group is write data transmitted to the controller from a host and randomized.

### Claim 12

A memory system comprising:
a nonvolatile memory; and
a controller that includes an encoder configured to encode a first group of data including a plurality of first data, each first data having a plurality of bits, and is configured to transmit the encoded first group of data, having a plurality of encoded data each having the same number of bits as the first data, to the nonvolatile memory via a plurality of data lines, wherein
the likelihood that the value in any of the bit positions of the first data is a first logical value is less than the likelihood that the value in any of the bit positions of the encoded data is the first logical value, and
a second logical value is less likely to be the value in an n-th bit position of the plurality of encoded data than in an m-th bit position of the plurality of encoded data that is adjacent to the n-th bit position.

### Claim 13 (depends on 12)

The memory system according to claim 12, wherein data written to the nonvolatile memory and each of the first data in the first group have randomized patterns.

### Claim 14 (depends on 12)

The memory system according to claim 12, wherein
the controller is configured to transmit to the nonvolatile memory each of the encoded data in the encoded first group of data over the data lines along with a flag that indicates whether or not the number of bits having the first logical value in the first data from which the encoded data was generated is less than the number of bits having the second logical value in the first data from which the encoded data was generated.

### Claim 15 (depends on 12)

The memory system according to claim 12, wherein
the nonvolatile memory includes memory cells in which data are stored and a decoder configured to convert each of the encoded data in the encoded first group of data into a second data, which are stored in the memory cells.

### Claim 16 (depends on 15)

The memory system according to claim 15, wherein
the nonvolatile memory includes an encoder configured to encode a third group of data read from the memory cells, and is configured to transmit the encoded third group of data to the controller via the plurality of data lines.

### Claim 17 (depends on 16)

The memory system according to claim 16, wherein
the nonvolatile memory further includes a switching circuit configured to switch connections between the encoder of the nonvolatile memory and the plurality of data lines, so that a particular bit of the encoded data output by the encoder of the nonvolatile memory is connectable to a predetermined one of the data lines.

### Claim 18 (depends on 16)

The memory system according to claim 16, wherein
the controller includes a decoder configured to decode each encoded data in the encoded third group of data into a fourth data, and output the fourth data.

### Claim 19 (depends on 18)

The memory system according to claim 18, wherein
the controller is configured to transmit the fourth data output from the decoder to a host.

### Claim 20 (depends on 12)

The memory system according to claim 12, wherein
the controller further includes a switching circuit configured to switch connections between the encoder of the controller and the plurality of data lines, so that a particular bit of the encoded data output by the encoder of the controller is connectable to a predetermined one of the data lines.