# US 12,008,245 B2 · Method and device for hot swapping memory, and memory

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- Number: US 12,008,245 B2
- Document ID: US12008245B2
- Status: Granted
- Kind: B2
- Application number: 17/821,760
- Filed: 2022-08-23
- Published: 2023-11-23
- Granted: 2024-06-11
- Earliest claimed: 2022-05-18
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Guowei Huang
- Web page: https://patentgrep.com/patent/US12008245B2

## CPC

- G06F 1/186: Securing of expansion boards in correspondence to slots provided at the computer enclosure
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/0673: {Single storage device}
- G06F 11/1441: {Resetting or repowering}
- G06F 11/1658: {Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit}
- G06F 13/4081: {Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for hot swapping a memory includes the following: in response to a triggering operation of a replacement key of an abnormal memory, data on the abnormal memory is copied to an idle memory when a system is powered on; and the abnormal memory is powered off and replaced with a new memory after the data is copied; and in response to the triggering operation of a power on key of the new memory, the new memory is powered on. A method for hot swapping a memory in the case where a system is not powered off is provided.

## Claims

### Claim 1

A memory, comprising
a memory body, and a replacement key and a power on key arranged on the memory body, wherein
the replacement key and the power on key are separately connected to a hub through an input/output interface; and the hub is configured to send a system management bus signal to a central processing unit (CPU) when level conversion occurs at the input/output interface; and
the CPU is configured to power on or power off the memory after receiving the system management bus signal.

### Claim 2 (depends on 1)

The memory of claim 1, further comprising
a first power supply and a first resistor, wherein
the input/output interface is grounded through the replacement key; the first power supply is arranged on a connecting line between the input/output interface and the replacement key; and the first resistor is arranged on a connecting line of the first power supply.

### Claim 3 (depends on 1)

The memory of claim 1, further comprising
a second power supply and a second resistor, wherein
the input/output interface is grounded through the power on key; the second power supply is arranged on the connecting line between the input/output interface and the power on key; and the second resistor is arranged on a connecting line of the second power supply.

### Claim 4 (depends on 1)

The memory of claim 1, further comprising
a third power supply, wherein
the input/output interface is grounded; and the replacement key is arranged between the third power supply and the input/output interface.

### Claim 5 (depends on 1)

The memory of claim 1, further comprising
a fourth power supply, wherein
the input/output interface is grounded; and the power on key is arranged between the fourth power supply and the input/output interface.

### Claim 6 (depends on 1)

The memory of claim 1, wherein
both the power on key and the replacement key are switches.

### Claim 7 (depends on 1)

The memory of claim 1, wherein
the CPU is connected to the power management IC of the memory; the CPU controls the memory to be powered off by pulling down the power management IC enable signal; and
the CPU controls the memory to be powered on by pulling up the power management IC enable signal.