# US 12,008,244 B2 · Secure non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,244 B2 - Document ID: US12008244B2 - Status: Granted - Kind: B2 - Application number: 17/810,093 - Filed: 2022-06-30 - Published: 2023-08-03 - Granted: 2024-06-11 - Earliest claimed: 2022-01-31 - Assignees: STMicroelectronics (Alps) SAS - Applicants: STMicroelectronics (Alps) SAS - Inventors: Jawad Benhammadi - Web page: https://patentgrep.com/patent/US12008244B2 ## CPC - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register. ## Claims ### Claim 1 A method, comprising: loading, from a non-volatile memory of a circuit to a computation circuit, a first security parameter of the circuit and a first error-correcting code stored in association with the first security parameter; verifying, by the computation circuit, the first security parameter and the first error-correcting code; determining whether one or more bits of the first security parameter are erroneous; loading the first security parameter into a register in response to determining that none of the bits of the first security parameter is erroneous; and loading a default value into the register in response to determining that two bits of the first security parameter are erroneous, the first security parameter and the default value defining access rules to the non-volatile memory. ### Claim 2 (depends on 1) The method of claim 1, wherein the default value corresponds to a value imposing a secure operating state on the circuit. ### Claim 3 (depends on 1) The method of claim 1, further comprising, in response to determining that two bits of the first security parameter are erroneous: transmitting an output signal from an interface of the non-volatile memory to a control circuit; and executing a countermeasure by the control circuit. ### Claim 4 (depends on 3) The method of claim 3, wherein the countermeasure comprises replacing a value of a cipher key stored in the non-volatile memory with a dummy value. ### Claim 5 (depends on 3) The method of claim 3, further comprising: incrementing, by the control circuit, a counter in response to receiving the output signal; and resetting the circuit in response to reaching a threshold value by the counter. ### Claim 6 (depends on 3) The method of claim 3, further comprising executing a second countermeasure by the interface in response to determining that two security parameter bits are erroneous. ### Claim 7 (depends on 3) The method of claim 3, further comprising: receiving, by the interface, a first control signal formed of m bits, capable of taking 2m different values, wherein only q values among these 2m values are authorized, wherein each of the q values is different by at least two-bit values, wherein m is greater than or equal to 2, and wherein q is smaller than or equal to 2m/2; comparing, by the interface, a value of the first control signal with each of the q values; and executing the countermeasure in response to the value of the first control signal corresponding to none of the q values. ### Claim 8 (depends on 7) The method of claim 7, wherein the executing comprises transmitting the output signal by the interface for controlling the circuit. ### Claim 9 (depends on 3) The method of claim 3, further comprising receiving, by the interface from the circuit, a warning input signal for controlling the circuit, the warning input signal indicating a detection of a suspicious event. ### Claim 10 (depends on 9) The method of claim 9, wherein the countermeasure comprises a ban of access to a first area of the non-volatile memory in response to receiving the warning input signal. ### Claim 11 (depends on 10) The method of claim 10, wherein the first area of the non-volatile memory contains at least one cipher key. ### Claim 12 (depends on 1) The method of claim 1, wherein the loading of the first security parameter is performed before an end of a circuit boot sequence. ### Claim 13 (depends on 1) The method of claim 1, wherein the non-volatile memory is a FLASH-type memory. ### Claim 14 A circuit, comprising: a non-volatile memory configured to store a first security parameter and a first error-correcting code, the first error-correcting code stored in association with the first security parameter; and a computation circuit configured to: verify the first security parameter and the first error-correcting code; determine whether one or more bits of the first security parameter are erroneous; load the first security parameter into a register in response to determining that none of the bits of the first security parameter is erroneous; and load a default value into the register in response to determining that two bits of the first security parameter are erroneous, the first security parameter and the default value defining access rules to the non-volatile memory. ### Claim 15 (depends on 14) The circuit of claim 14, wherein the circuit further comprises a control circuit configured to execute a countermeasure. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the non-volatile memory comprises an interface, the interface configured to transmit an output signal to the control circuit in response to determining that two bits of the first security parameter are erroneous, the output signal configured to indicate to the control circuit to execute the countermeasure. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the countermeasure comprises replacing a value of a cipher key stored in the non-volatile memory with a dummy value. ### Claim 18 A device, comprising a circuit, the circuit comprising: a non-volatile memory configured to store a first security parameter and a first error-correcting code, the first error-correcting code stored in association with the first security parameter; and a computation circuit configured to: verify the first security parameter and the first error-correcting code; determine whether one or more bits of the first security parameter are erroneous; load the first security parameter into a register in response to determining that none of the bits of the first security parameter is erroneous; and load a default value into the register in response to determining that two bits of the first security parameter are erroneous, the first security parameter and the default value defining access rules to the non-volatile memory. ### Claim 19 (depends on 18) The device of claim 18, wherein the circuit further comprises a control circuit configured to execute a countermeasure. ### Claim 20 (depends on 19) The device of claim 19, wherein the non-volatile memory comprises an interface, the interface configured to transmit an output signal to the control circuit in response to determining that two bits of the first security parameter are erroneous, the output signal configured to indicate to the control circuit to execute the countermeasure. ### Claim 21 (depends on 19) The device of claim 19, wherein access to an area of the non-volatile memory is authorized in response to the first security parameter being stored in the register, and wherein access to the area of the non-volatile memory is unauthorized in response to the default value being stored in the register. ### Claim 22 (depends on 1) The method of claim 1, wherein access to an area of the non-volatile memory is authorized in response to the first security parameter being stored in the register, and wherein access to the area of the non-volatile memory is unauthorized in response to the default value being stored in the register. ### Claim 23 (depends on 14) The circuit of claim 14, wherein access to an area of the non-volatile memory is authorized in response to the first security parameter being stored in the register, and wherein access to the area of the non-volatile memory is unauthorized in response to the default value being stored in the register.