# US 12,008,243 B2 · Reducing index update messages for memory-based communication queues

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- Number: US 12,008,243 B2
- Document ID: US12008243B2
- Status: Granted
- Kind: B2
- Application number: 17/979,390
- Filed: 2022-11-02
- Published: 2024-05-02
- Granted: 2024-06-11
- Earliest claimed: 2022-11-02
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Michael Keith Dugan; Tony M. Brewer
- Web page: https://patentgrep.com/patent/US12008243B2

## CPC

- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system includes a host device, a memory device, and a command manager configured to reorder respective command responses for corresponding commands between the host device and the memory device. The command manager is further configured to receive a command response associated with a transaction identifier for each command. An index value for the command is written to a reordering queue. In response to a command response write for the command response, the index value from the reordering queue is read. The index value is written in an index update queue. A network write index update message is transmitted.

## Claims

### Claim 1

A system, comprising:
a host device;
a memory device; and
a command manager configured to reorder respective command responses for corresponding commands between the host device and the memory device, the command manager is further configured to:
receive a command response associated with a transaction identifier for each command;
write an index value for the command to a reordering queue; and
in response to a command response write for the command response:
read the index value from the reordering queue;
write the index value to an index update queue; and
transmit a network write index update message.

### Claim 2 (depends on 1)

The system of claim 1, wherein the host device is coupled to the memory device using a compute express link (CXL) interconnect.

### Claim 3 (depends on 1)

The system of claim 1, wherein the reordering queue is a set of circular reordering queues.

### Claim 4 (depends on 1)

The system of claim 1, wherein the reordering queue is a set of 32 circular reordering queues.

### Claim 5 (depends on 1)

The system of claim 1, wherein the index update queue is a set of circular index update queues.

### Claim 6 (depends on 1)

The system of claim 1, wherein the index update queue is a set of 32 circular index update queues.

### Claim 7 (depends on 1)

The system of claim 1, wherein the command manager is further configured to reorder command responses to an order in which the commands were issued using the reordering queue.

### Claim 8 (depends on 1)

The system of claim 1, wherein the index update queue is configured to store index values in an order in which the associated commands were issued.

### Claim 9 (depends on 1)

The system of claim 1, wherein the command manager is further configured to allocate a free list entry for the command from a free list, the free list entry associated with the transaction identifier of the command.

### Claim 10 (depends on 1)

The system of claim 1, wherein in response to writing the index value to the index update queue, the command manager is configured to set a valid bit corresponding to a corresponding index update queue entry.

### Claim 11 (depends on 1)

The system of claim 1, wherein the command manager is further configured to transmit index update messages one at a time.

### Claim 12

A method, comprising:
for each command of a plurality of commands, receiving a command response associated with a transaction identifier;
writing an index value for the command response to a reordering queue; and
in response to a command response write for the command response:
reading the index value from the reordering queue;
writing the index value to an index update queue based on a temporal order that the command response was received; and
transmitting a network write index update message for the command response.

### Claim 13 (depends on 12)

The method of claim 12, wherein the index update queue is a set of 32 circular queues.

### Claim 14 (depends on 12)

The method of claim 12, wherein the index update queue is configured to store index values in an order in which the associated commands were issued.

### Claim 15 (depends on 12)

The method of claim 12, further comprising allocating a free list entry for the command from a free list, the free list entry associated with the transaction identifier of the command.

### Claim 16 (depends on 12)

The method of claim 12, further comprising in response to writing the index value to the index update queue setting a valid bit for a corresponding index update queue entry.

### Claim 17 (depends on 16)

The method of claim 16, further comprising in response to setting the valid bit for the index update queue entry, determining a number of entries in the index update queue that have the valid bit set.

### Claim 18 (depends on 17)

The method of claim 17, in response to determining that one entry in the index update queue has the valid bit set, transmitting a new index update message corresponding to the one entry in the index update queue.

### Claim 19 (depends on 17)

The method of claim 17, in response to determining that more than one entry in the index update queue has the valid bit set:
transmitting a new index update message corresponding to a valid tail entry of the index update queue; and
discarding remaining valid entries in the index update queue.

### Claim 20

At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processor circuit of a memory system, cause the processor circuit to perform operations comprising:
for each command of a plurality of commands, receiving a command response associated with a transaction identifier;
writing an index value for the command response to a reordering queue; and
in response to a command response write for the command response:
reading the index value from the reordering queue and;
writing the index value to an index update queue based on a temporal order that the command response was received; and
transmitting a network write index update message for the command response.